Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Lochnagar clock control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2017-2018 Cirrus Logic, Inc. and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *                         Cirrus Logic International Semiconductor Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Author: Charles Keepax <ckeepax@opensource.cirrus.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/mfd/lochnagar1_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/mfd/lochnagar2_regs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <dt-bindings/clk/lochnagar.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define LOCHNAGAR_NUM_CLOCKS	(LOCHNAGAR_SPDIF_CLKOUT + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) struct lochnagar_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	const char * const name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	struct lochnagar_clk_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	u16 cfg_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	u16 ena_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	u16 src_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	u16 src_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) struct lochnagar_clk_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	struct lochnagar_clk lclks[LOCHNAGAR_NUM_CLOCKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define LN_PARENT(NAME) { .name = NAME, .fw_name = NAME }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static const struct clk_parent_data lochnagar1_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	LN_PARENT("ln-none"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	LN_PARENT("ln-spdif-mclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	LN_PARENT("ln-psia1-mclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	LN_PARENT("ln-psia2-mclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	LN_PARENT("ln-cdc-clkout"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	LN_PARENT("ln-dsp-clkout"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	LN_PARENT("ln-pmic-32k"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	LN_PARENT("ln-gf-mclk1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	LN_PARENT("ln-gf-mclk3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	LN_PARENT("ln-gf-mclk2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	LN_PARENT("ln-gf-mclk4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static const struct clk_parent_data lochnagar2_clk_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	LN_PARENT("ln-none"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	LN_PARENT("ln-cdc-clkout"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	LN_PARENT("ln-dsp-clkout"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	LN_PARENT("ln-pmic-32k"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	LN_PARENT("ln-spdif-mclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	LN_PARENT("ln-clk-12m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	LN_PARENT("ln-clk-11m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	LN_PARENT("ln-clk-24m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	LN_PARENT("ln-clk-22m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	LN_PARENT("ln-clk-8m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	LN_PARENT("ln-usb-clk-24m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	LN_PARENT("ln-gf-mclk1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	LN_PARENT("ln-gf-mclk3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	LN_PARENT("ln-gf-mclk2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	LN_PARENT("ln-psia1-mclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	LN_PARENT("ln-psia2-mclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	LN_PARENT("ln-spdif-clkout"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	LN_PARENT("ln-adat-mclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	LN_PARENT("ln-usb-clk-12m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define LN1_CLK(ID, NAME, REG) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	[LOCHNAGAR_##ID] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		.name = NAME, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		.cfg_reg = LOCHNAGAR1_##REG, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		.ena_mask = LOCHNAGAR1_##ID##_ENA_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		.src_reg = LOCHNAGAR1_##ID##_SEL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		.src_mask = LOCHNAGAR1_SRC_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define LN2_CLK(ID, NAME) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	[LOCHNAGAR_##ID] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		.name = NAME, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		.cfg_reg = LOCHNAGAR2_##ID##_CTRL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		.src_reg = LOCHNAGAR2_##ID##_CTRL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		.ena_mask = LOCHNAGAR2_CLK_ENA_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		.src_mask = LOCHNAGAR2_CLK_SRC_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const struct lochnagar_clk lochnagar1_clks[LOCHNAGAR_NUM_CLOCKS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	LN1_CLK(CDC_MCLK1,      "ln-cdc-mclk1",  CDC_AIF_CTRL2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	LN1_CLK(CDC_MCLK2,      "ln-cdc-mclk2",  CDC_AIF_CTRL2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	LN1_CLK(DSP_CLKIN,      "ln-dsp-clkin",  DSP_AIF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	LN1_CLK(GF_CLKOUT1,     "ln-gf-clkout1", GF_AIF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static const struct lochnagar_clk lochnagar2_clks[LOCHNAGAR_NUM_CLOCKS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	LN2_CLK(CDC_MCLK1,      "ln-cdc-mclk1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	LN2_CLK(CDC_MCLK2,      "ln-cdc-mclk2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	LN2_CLK(DSP_CLKIN,      "ln-dsp-clkin"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	LN2_CLK(GF_CLKOUT1,     "ln-gf-clkout1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	LN2_CLK(GF_CLKOUT2,     "ln-gf-clkout2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	LN2_CLK(PSIA1_MCLK,     "ln-psia1-mclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	LN2_CLK(PSIA2_MCLK,     "ln-psia2-mclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	LN2_CLK(SPDIF_MCLK,     "ln-spdif-mclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	LN2_CLK(ADAT_MCLK,      "ln-adat-mclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	LN2_CLK(SOUNDCARD_MCLK, "ln-soundcard-mclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct lochnagar_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	const struct clk_parent_data *parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	int nparents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	const struct lochnagar_clk *clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const struct lochnagar_config lochnagar1_conf = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	.parents = lochnagar1_clk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	.nparents = ARRAY_SIZE(lochnagar1_clk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	.clks = lochnagar1_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const struct lochnagar_config lochnagar2_conf = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	.parents = lochnagar2_clk_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.nparents = ARRAY_SIZE(lochnagar2_clk_parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.clks = lochnagar2_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static inline struct lochnagar_clk *lochnagar_hw_to_lclk(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	return container_of(hw, struct lochnagar_clk, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int lochnagar_clk_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	struct lochnagar_clk *lclk = lochnagar_hw_to_lclk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	struct lochnagar_clk_priv *priv = lclk->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	struct regmap *regmap = priv->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	ret = regmap_update_bits(regmap, lclk->cfg_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 				 lclk->ena_mask, lclk->ena_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		dev_dbg(priv->dev, "Failed to prepare %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			lclk->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static void lochnagar_clk_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct lochnagar_clk *lclk = lochnagar_hw_to_lclk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	struct lochnagar_clk_priv *priv = lclk->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	struct regmap *regmap = priv->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	ret = regmap_update_bits(regmap, lclk->cfg_reg, lclk->ena_mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		dev_dbg(priv->dev, "Failed to unprepare %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			lclk->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int lochnagar_clk_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	struct lochnagar_clk *lclk = lochnagar_hw_to_lclk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	struct lochnagar_clk_priv *priv = lclk->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct regmap *regmap = priv->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	ret = regmap_update_bits(regmap, lclk->src_reg, lclk->src_mask, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		dev_dbg(priv->dev, "Failed to reparent %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 			lclk->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static u8 lochnagar_clk_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	struct lochnagar_clk *lclk = lochnagar_hw_to_lclk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	struct lochnagar_clk_priv *priv = lclk->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	struct regmap *regmap = priv->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	ret = regmap_read(regmap, lclk->src_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		dev_dbg(priv->dev, "Failed to read parent of %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			lclk->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		return clk_hw_get_num_parents(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	val &= lclk->src_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const struct clk_ops lochnagar_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	.prepare = lochnagar_clk_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.unprepare = lochnagar_clk_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.set_parent = lochnagar_clk_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.get_parent = lochnagar_clk_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static struct clk_hw *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) lochnagar_of_clk_hw_get(struct of_phandle_args *clkspec, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	struct lochnagar_clk_priv *priv = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	unsigned int idx = clkspec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (idx >= ARRAY_SIZE(priv->lclks)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		dev_err(priv->dev, "Invalid index %u\n", idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	return &priv->lclks[idx].hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static const struct of_device_id lochnagar_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	{ .compatible = "cirrus,lochnagar1-clk", .data = &lochnagar1_conf },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	{ .compatible = "cirrus,lochnagar2-clk", .data = &lochnagar2_conf },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MODULE_DEVICE_TABLE(of, lochnagar_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int lochnagar_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	struct clk_init_data clk_init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		.ops = &lochnagar_clk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	struct lochnagar_clk_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	struct lochnagar_clk *lclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	struct lochnagar_config *conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	of_id = of_match_device(lochnagar_of_match, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (!of_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	priv->regmap = dev_get_regmap(dev->parent, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	conf = (struct lochnagar_config *)of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	memcpy(priv->lclks, conf->clks, sizeof(priv->lclks));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	clk_init.parent_data = conf->parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	clk_init.num_parents = conf->nparents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	for (i = 0; i < ARRAY_SIZE(priv->lclks); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		lclk = &priv->lclks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		if (!lclk->name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		clk_init.name = lclk->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		lclk->priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		lclk->hw.init = &clk_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		ret = devm_clk_hw_register(dev, &lclk->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 			dev_err(dev, "Failed to register %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 				lclk->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	ret = devm_of_clk_add_hw_provider(dev, lochnagar_of_clk_hw_get, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		dev_err(dev, "Failed to register provider: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static struct platform_driver lochnagar_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		.name = "lochnagar-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		.of_match_table = lochnagar_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	.probe = lochnagar_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) module_platform_driver(lochnagar_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) MODULE_AUTHOR("Charles Keepax <ckeepax@opensource.cirrus.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MODULE_DESCRIPTION("Clock driver for Cirrus Logic Lochnagar Board");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MODULE_LICENSE("GPL v2");