^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Synopsys HSDK SDP Generic PLL clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2017 Synopsys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CGU_PLL_CTRL 0x000 /* ARC PLL control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CGU_PLL_STATUS 0x004 /* ARC PLL status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CGU_PLL_FMEAS 0x008 /* ARC PLL frequency measurement register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CGU_PLL_MON 0x00C /* ARC PLL monitor register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CGU_PLL_CTRL_ODIV_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CGU_PLL_CTRL_IDIV_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CGU_PLL_CTRL_FBDIV_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CGU_PLL_CTRL_BAND_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CGU_PLL_CTRL_ODIV_MASK GENMASK(3, CGU_PLL_CTRL_ODIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CGU_PLL_CTRL_IDIV_MASK GENMASK(8, CGU_PLL_CTRL_IDIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CGU_PLL_CTRL_FBDIV_MASK GENMASK(15, CGU_PLL_CTRL_FBDIV_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CGU_PLL_CTRL_PD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CGU_PLL_CTRL_BYPASS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CGU_PLL_STATUS_LOCK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CGU_PLL_STATUS_ERR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HSDK_PLL_MAX_LOCK_TIME 100 /* 100 us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CGU_PLL_SOURCE_MAX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CORE_IF_CLK_THRESHOLD_HZ 500000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CREG_CORE_IF_CLK_DIV_1 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CREG_CORE_IF_CLK_DIV_2 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct hsdk_pll_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 idiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 fbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 odiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 band;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { 100000000, 0, 11, 3, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { 133000000, 0, 15, 3, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { 200000000, 1, 47, 3, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) { 233000000, 1, 27, 2, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { 300000000, 1, 35, 2, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) { 333000000, 1, 39, 2, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { 400000000, 1, 47, 2, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) { 500000000, 0, 14, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) { 600000000, 0, 17, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) { 700000000, 0, 20, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { 800000000, 0, 23, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { 900000000, 1, 26, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) { 1000000000, 1, 29, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { 1100000000, 1, 32, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { 1200000000, 1, 35, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { 1300000000, 1, 38, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { 1400000000, 1, 41, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { 1500000000, 1, 44, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { 1600000000, 1, 47, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { 27000000, 0, 0, 0, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { 148500000, 0, 21, 3, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { 297000000, 0, 21, 2, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { 540000000, 0, 19, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { 594000000, 0, 21, 1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct hsdk_pll_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) void __iomem *spec_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) const struct hsdk_pll_devdata *pll_devdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct hsdk_pll_devdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) const struct hsdk_pll_cfg *pll_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int (*update_rate)(struct hsdk_pll_clk *clk, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) const struct hsdk_pll_cfg *cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int hsdk_pll_core_update_rate(struct hsdk_pll_clk *, unsigned long,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) const struct hsdk_pll_cfg *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int hsdk_pll_comm_update_rate(struct hsdk_pll_clk *, unsigned long,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) const struct hsdk_pll_cfg *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static const struct hsdk_pll_devdata core_pll_devdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .pll_cfg = asdt_pll_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .update_rate = hsdk_pll_core_update_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static const struct hsdk_pll_devdata sdt_pll_devdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .pll_cfg = asdt_pll_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .update_rate = hsdk_pll_comm_update_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const struct hsdk_pll_devdata hdmi_pll_devdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .pll_cfg = hdmi_pll_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .update_rate = hsdk_pll_comm_update_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static inline void hsdk_pll_write(struct hsdk_pll_clk *clk, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) iowrite32(val, clk->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static inline u32 hsdk_pll_read(struct hsdk_pll_clk *clk, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return ioread32(clk->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static inline void hsdk_pll_set_cfg(struct hsdk_pll_clk *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) const struct hsdk_pll_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (cfg->bypass) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) val = hsdk_pll_read(clk, CGU_PLL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) val |= CGU_PLL_CTRL_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Powerdown and Bypass bits should be cleared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) val |= cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) val |= cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) val |= cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dev_dbg(clk->dev, "write configuration: %#x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) hsdk_pll_write(clk, CGU_PLL_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static inline bool hsdk_pll_is_locked(struct hsdk_pll_clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_LOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static inline bool hsdk_pll_is_err(struct hsdk_pll_clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_ERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static inline struct hsdk_pll_clk *to_hsdk_pll_clk(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return container_of(hw, struct hsdk_pll_clk, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static unsigned long hsdk_pll_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u64 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 idiv, fbdiv, odiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct hsdk_pll_clk *clk = to_hsdk_pll_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) val = hsdk_pll_read(clk, CGU_PLL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) dev_dbg(clk->dev, "current configuration: %#x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Check if PLL is bypassed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (val & CGU_PLL_CTRL_BYPASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Check if PLL is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (val & CGU_PLL_CTRL_PD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* input divider = reg.idiv + 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* fb divider = 2*(reg.fbdiv + 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) fbdiv = 2 * (1 + ((val & CGU_PLL_CTRL_FBDIV_MASK) >> CGU_PLL_CTRL_FBDIV_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* output divider = 2^(reg.odiv) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) odiv = 1 << ((val & CGU_PLL_CTRL_ODIV_MASK) >> CGU_PLL_CTRL_ODIV_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) rate = (u64)parent_rate * fbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) do_div(rate, idiv * odiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static long hsdk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned long best_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct hsdk_pll_clk *clk = to_hsdk_pll_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) const struct hsdk_pll_cfg *pll_cfg = clk->pll_devdata->pll_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (pll_cfg[0].rate == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) best_rate = pll_cfg[0].rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) for (i = 1; pll_cfg[i].rate != 0; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) best_rate = pll_cfg[i].rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) dev_dbg(clk->dev, "chosen best rate: %lu\n", best_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return best_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static int hsdk_pll_comm_update_rate(struct hsdk_pll_clk *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) const struct hsdk_pll_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) hsdk_pll_set_cfg(clk, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * Wait until CGU relocks and check error status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * If after timeout CGU is unlocked yet return error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) udelay(HSDK_PLL_MAX_LOCK_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (!hsdk_pll_is_locked(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (hsdk_pll_is_err(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int hsdk_pll_core_update_rate(struct hsdk_pll_clk *clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) const struct hsdk_pll_cfg *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * When core clock exceeds 500MHz, the divider for the interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * clock must be programmed to div-by-2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (rate > CORE_IF_CLK_THRESHOLD_HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) iowrite32(CREG_CORE_IF_CLK_DIV_2, clk->spec_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) hsdk_pll_set_cfg(clk, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * Wait until CGU relocks and check error status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * If after timeout CGU is unlocked yet return error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) udelay(HSDK_PLL_MAX_LOCK_TIME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (!hsdk_pll_is_locked(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (hsdk_pll_is_err(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * Program divider to div-by-1 if we succesfuly set core clock below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * 500MHz threshold.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (rate <= CORE_IF_CLK_THRESHOLD_HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) iowrite32(CREG_CORE_IF_CLK_DIV_1, clk->spec_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int hsdk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct hsdk_pll_clk *clk = to_hsdk_pll_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) const struct hsdk_pll_cfg *pll_cfg = clk->pll_devdata->pll_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) for (i = 0; pll_cfg[i].rate != 0; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (pll_cfg[i].rate == rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return clk->pll_devdata->update_rate(clk, rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) &pll_cfg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) dev_err(clk->dev, "invalid rate=%ld, parent_rate=%ld\n", rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const struct clk_ops hsdk_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .recalc_rate = hsdk_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .round_rate = hsdk_pll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .set_rate = hsdk_pll_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static int hsdk_pll_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct resource *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned int num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct hsdk_pll_clk *pll_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct clk_init_data init = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (!pll_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) pll_clk->regs = devm_ioremap_resource(dev, mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (IS_ERR(pll_clk->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return PTR_ERR(pll_clk->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) init.name = dev->of_node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) init.ops = &hsdk_pll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) parent_name = of_clk_get_parent_name(dev->of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) num_parents = of_clk_get_parent_count(dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (num_parents == 0 || num_parents > CGU_PLL_SOURCE_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dev_err(dev, "wrong clock parents number: %u\n", num_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) init.num_parents = num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) pll_clk->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) pll_clk->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) pll_clk->pll_devdata = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (!pll_clk->pll_devdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dev_err(dev, "No OF match data provided\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ret = devm_clk_hw_register(dev, &pll_clk->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) dev_err(dev, "failed to register %s clock\n", init.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) &pll_clk->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int hsdk_pll_clk_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) of_clk_del_provider(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static void __init of_hsdk_pll_clk_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) unsigned int num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct hsdk_pll_clk *pll_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct clk_init_data init = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (!pll_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) pll_clk->regs = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (!pll_clk->regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) pr_err("failed to map pll registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) goto err_free_pll_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) pll_clk->spec_regs = of_iomap(node, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (!pll_clk->spec_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) pr_err("failed to map pll registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) goto err_unmap_comm_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) init.name = node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) init.ops = &hsdk_pll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) parent_name = of_clk_get_parent_name(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) num_parents = of_clk_get_parent_count(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (num_parents > CGU_PLL_SOURCE_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) pr_err("too much clock parents: %u\n", num_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) goto err_unmap_spec_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) init.num_parents = num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) pll_clk->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) pll_clk->pll_devdata = &core_pll_devdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ret = clk_hw_register(NULL, &pll_clk->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) pr_err("failed to register %pOFn clock\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) goto err_unmap_spec_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clk->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) pr_err("failed to add hw provider for %pOFn clock\n", node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) goto err_unmap_spec_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) err_unmap_spec_regs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) iounmap(pll_clk->spec_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) err_unmap_comm_regs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) iounmap(pll_clk->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) err_free_pll_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) kfree(pll_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Core PLL needed early for ARC cpus timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) CLK_OF_DECLARE(hsdk_pll_clock, "snps,hsdk-core-pll-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) of_hsdk_pll_clk_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static const struct of_device_id hsdk_pll_clk_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) { .compatible = "snps,hsdk-gp-pll-clock", .data = &sdt_pll_devdata},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) { .compatible = "snps,hsdk-hdmi-pll-clock", .data = &hdmi_pll_devdata},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static struct platform_driver hsdk_pll_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .name = "hsdk-gp-pll-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .of_match_table = hsdk_pll_clk_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .probe = hsdk_pll_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .remove = hsdk_pll_clk_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) builtin_platform_driver(hsdk_pll_clk_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags