^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2011-2012 Calxeda, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define HB_PLL_LOCK_500 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define HB_PLL_LOCK 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define HB_PLL_DIVF_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define HB_PLL_DIVF_MASK 0x0ff00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define HB_PLL_DIVQ_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define HB_PLL_DIVQ_MASK 0x00070000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define HB_PLL_DIVR_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HB_PLL_DIVR_MASK 0x00001f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HB_PLL_RANGE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HB_PLL_RANGE_MASK 0x00000070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HB_PLL_BYPASS 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HB_PLL_RESET 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HB_PLL_EXT_BYPASS 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HB_PLL_EXT_ENA 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define HB_PLL_VCO_MIN_FREQ 2133000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HB_PLL_MAX_FREQ HB_PLL_VCO_MIN_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HB_PLL_MIN_FREQ (HB_PLL_VCO_MIN_FREQ / 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HB_A9_BCLK_DIV_MASK 0x00000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HB_A9_BCLK_DIV_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HB_A9_PCLK_DIV 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct hb_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define to_hb_clk(p) container_of(p, struct hb_clk, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static int clk_pll_prepare(struct clk_hw *hwclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct hb_clk *hbclk = to_hb_clk(hwclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) reg = readl(hbclk->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) reg &= ~HB_PLL_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) writel(reg, hbclk->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static void clk_pll_unprepare(struct clk_hw *hwclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct hb_clk *hbclk = to_hb_clk(hwclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) reg = readl(hbclk->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) reg |= HB_PLL_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) writel(reg, hbclk->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int clk_pll_enable(struct clk_hw *hwclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct hb_clk *hbclk = to_hb_clk(hwclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) reg = readl(hbclk->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) reg |= HB_PLL_EXT_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) writel(reg, hbclk->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void clk_pll_disable(struct clk_hw *hwclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct hb_clk *hbclk = to_hb_clk(hwclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) reg = readl(hbclk->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) reg &= ~HB_PLL_EXT_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) writel(reg, hbclk->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct hb_clk *hbclk = to_hb_clk(hwclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned long divf, divq, vco_freq, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) reg = readl(hbclk->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (reg & HB_PLL_EXT_BYPASS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) divf = (reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) divq = (reg & HB_PLL_DIVQ_MASK) >> HB_PLL_DIVQ_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) vco_freq = parent_rate * (divf + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return vco_freq / (1 << divq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static void clk_pll_calc(unsigned long rate, unsigned long ref_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 *pdivq, u32 *pdivf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 divq, divf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned long vco_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (rate < HB_PLL_MIN_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) rate = HB_PLL_MIN_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (rate > HB_PLL_MAX_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) rate = HB_PLL_MAX_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) for (divq = 1; divq <= 6; divq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if ((rate * (1 << divq)) >= HB_PLL_VCO_MIN_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) vco_freq = rate * (1 << divq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) divf = (vco_freq + (ref_freq / 2)) / ref_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) divf--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) *pdivq = divq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) *pdivf = divf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static long clk_pll_round_rate(struct clk_hw *hwclk, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 divq, divf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned long ref_freq = *parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) clk_pll_calc(rate, ref_freq, &divq, &divf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return (ref_freq * (divf + 1)) / (1 << divq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct hb_clk *hbclk = to_hb_clk(hwclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 divq, divf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) clk_pll_calc(rate, parent_rate, &divq, &divf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) reg = readl(hbclk->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (divf != ((reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Need to re-lock PLL, so put it into bypass mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) reg |= HB_PLL_EXT_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) writel(reg | HB_PLL_RESET, hbclk->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) reg &= ~(HB_PLL_DIVF_MASK | HB_PLL_DIVQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) reg |= (divf << HB_PLL_DIVF_SHIFT) | (divq << HB_PLL_DIVQ_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) writel(reg | HB_PLL_RESET, hbclk->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) writel(reg, hbclk->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) reg |= HB_PLL_EXT_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) reg &= ~HB_PLL_EXT_BYPASS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) reg &= ~HB_PLL_DIVQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) reg |= divq << HB_PLL_DIVQ_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) writel(reg, hbclk->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const struct clk_ops clk_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .prepare = clk_pll_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .unprepare = clk_pll_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .enable = clk_pll_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .disable = clk_pll_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .recalc_rate = clk_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .round_rate = clk_pll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .set_rate = clk_pll_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static unsigned long clk_cpu_periphclk_recalc_rate(struct clk_hw *hwclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct hb_clk *hbclk = to_hb_clk(hwclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 div = (readl(hbclk->reg) & HB_A9_PCLK_DIV) ? 8 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return parent_rate / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const struct clk_ops a9periphclk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .recalc_rate = clk_cpu_periphclk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static unsigned long clk_cpu_a9bclk_recalc_rate(struct clk_hw *hwclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct hb_clk *hbclk = to_hb_clk(hwclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 div = (readl(hbclk->reg) & HB_A9_BCLK_DIV_MASK) >> HB_A9_BCLK_DIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return parent_rate / (div + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static const struct clk_ops a9bclk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .recalc_rate = clk_cpu_a9bclk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct hb_clk *hbclk = to_hb_clk(hwclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) div = readl(hbclk->reg) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) div++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) div *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return parent_rate / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static long clk_periclk_round_rate(struct clk_hw *hwclk, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) div = *parent_rate / rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) div++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) div &= ~0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return *parent_rate / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int clk_periclk_set_rate(struct clk_hw *hwclk, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct hb_clk *hbclk = to_hb_clk(hwclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) div = parent_rate / rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (div & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) writel(div >> 1, hbclk->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static const struct clk_ops periclk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .recalc_rate = clk_periclk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .round_rate = clk_periclk_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .set_rate = clk_periclk_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static void __init hb_clk_init(struct device_node *node, const struct clk_ops *ops, unsigned long clkflags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct hb_clk *hb_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) const char *clk_name = node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct device_node *srnp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) rc = of_property_read_u32(node, "reg", ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (WARN_ON(rc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) hb_clk = kzalloc(sizeof(*hb_clk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (WARN_ON(!hb_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Map system registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) srnp = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) hb_clk->reg = of_iomap(srnp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) of_node_put(srnp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) BUG_ON(!hb_clk->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) hb_clk->reg += reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) of_property_read_string(node, "clock-output-names", &clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) init.name = clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) init.ops = ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) init.flags = clkflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) parent_name = of_clk_get_parent_name(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) hb_clk->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) rc = clk_hw_register(NULL, &hb_clk->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (WARN_ON(rc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) kfree(hb_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) of_clk_add_hw_provider(node, of_clk_hw_simple_get, &hb_clk->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static void __init hb_pll_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) hb_clk_init(node, &clk_pll_ops, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) CLK_OF_DECLARE(hb_pll, "calxeda,hb-pll-clock", hb_pll_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static void __init hb_a9periph_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) hb_clk_init(node, &a9periphclk_ops, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) CLK_OF_DECLARE(hb_a9periph, "calxeda,hb-a9periph-clock", hb_a9periph_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static void __init hb_a9bus_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) hb_clk_init(node, &a9bclk_ops, CLK_IS_CRITICAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) CLK_OF_DECLARE(hb_a9bus, "calxeda,hb-a9bus-clock", hb_a9bus_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static void __init hb_emmc_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) hb_clk_init(node, &periclk_ops, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) CLK_OF_DECLARE(hb_emmc, "calxeda,hb-emmc-clock", hb_emmc_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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