^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Clock driver for Hi655x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2017, Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Daniel Lezcano <daniel.lezcano@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mfd/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mfd/hi655x-pmic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define HI655X_CLK_BASE HI655X_BUS_ADDR(0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define HI655X_CLK_SET BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct hi655x_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct hi655x_pmic *hi655x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct clk_hw clk_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static unsigned long hi655x_clk_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) return 32768;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static int hi655x_clk_enable(struct clk_hw *hw, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct hi655x_clk *hi655x_clk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) container_of(hw, struct hi655x_clk, clk_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct hi655x_pmic *hi655x = hi655x_clk->hi655x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) return regmap_update_bits(hi655x->regmap, HI655X_CLK_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) HI655X_CLK_SET, enable ? HI655X_CLK_SET : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int hi655x_clk_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return hi655x_clk_enable(hw, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static void hi655x_clk_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) hi655x_clk_enable(hw, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static int hi655x_clk_is_prepared(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct hi655x_clk *hi655x_clk =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) container_of(hw, struct hi655x_clk, clk_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct hi655x_pmic *hi655x = hi655x_clk->hi655x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) uint32_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ret = regmap_read(hi655x->regmap, HI655X_CLK_BASE, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return val & HI655X_CLK_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static const struct clk_ops hi655x_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .prepare = hi655x_clk_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .unprepare = hi655x_clk_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .is_prepared = hi655x_clk_is_prepared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .recalc_rate = hi655x_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int hi655x_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct device *parent = pdev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct hi655x_pmic *hi655x = dev_get_drvdata(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct hi655x_clk *hi655x_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) const char *clk_name = "hi655x-clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct clk_init_data init = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .name = clk_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .ops = &hi655x_clk_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) hi655x_clk = devm_kzalloc(&pdev->dev, sizeof(*hi655x_clk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (!hi655x_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) of_property_read_string_index(parent->of_node, "clock-output-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 0, &clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) hi655x_clk->clk_hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) hi655x_clk->hi655x = hi655x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) platform_set_drvdata(pdev, hi655x_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ret = devm_clk_hw_register(&pdev->dev, &hi655x_clk->clk_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_simple_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) &hi655x_clk->clk_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static struct platform_driver hi655x_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .probe = hi655x_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .name = "hi655x-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) module_platform_driver(hi655x_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MODULE_DESCRIPTION("Clk driver for the hi655x series PMICs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MODULE_AUTHOR("Daniel Lezcano <daniel.lezcano@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MODULE_ALIAS("platform:hi655x-clk");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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