^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Cortina Gemini SoC Clock Controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2017 Linus Walleij <linus.walleij@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define pr_fmt(fmt) "clk-gemini: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <dt-bindings/reset/cortina,gemini-reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <dt-bindings/clock/cortina,gemini-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Globally visible clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static DEFINE_SPINLOCK(gemini_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GEMINI_GLOBAL_STATUS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PLL_OSC_SEL BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AHBSPEED_SHIFT (15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AHBSPEED_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CPU_AHB_RATIO_SHIFT (18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CPU_AHB_RATIO_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define GEMINI_GLOBAL_PLL_CONTROL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define GEMINI_GLOBAL_SOFT_RESET 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define GEMINI_GLOBAL_MISC_CONTROL 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PCI_CLK_66MHZ BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GEMINI_GLOBAL_CLOCK_CONTROL 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PCI_CLKRUN_EN BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TVC_HALFDIV_SHIFT (24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TVC_HALFDIV_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SECURITY_CLK_SEL BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GEMINI_GLOBAL_PCI_DLL_CONTROL 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PCI_DLL_BYPASS BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCI_DLL_TAP_SEL_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * struct gemini_data_data - Gemini gated clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @bit_idx: the bit used to gate this clock in the clock register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @name: the clock name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @parent_name: the name of the parent clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @flags: standard clock framework flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct gemini_gate_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u8 bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * struct clk_gemini_pci - Gemini PCI clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @hw: corresponding clock hardware entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @map: regmap to access the registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @rate: current rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct clk_gemini_pci {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * struct gemini_reset - gemini reset controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @map: regmap to access the containing system controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * @rcdev: reset controller device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct gemini_reset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct reset_controller_dev rcdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Keeps track of all clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static struct clk_hw_onecell_data *gemini_clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static const struct gemini_gate_data gemini_gates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { 1, "security-gate", "secdiv", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { 2, "gmac0-gate", "ahb", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { 3, "gmac1-gate", "ahb", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { 4, "sata0-gate", "ahb", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { 5, "sata1-gate", "ahb", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { 6, "usb0-gate", "ahb", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { 7, "usb1-gate", "ahb", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { 8, "ide-gate", "ahb", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { 9, "pci-gate", "ahb", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * The DDR controller may never have a driver, but certainly must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * not be gated off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { 10, "ddr-gate", "ahb", CLK_IS_CRITICAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * The flash controller must be on to access NOR flash through the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * memory map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { 11, "flash-gate", "ahb", CLK_IGNORE_UNUSED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) { 12, "tvc-gate", "ahb", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { 13, "boot-gate", "apb", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define to_pciclk(_hw) container_of(_hw, struct clk_gemini_pci, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define to_gemini_reset(p) container_of((p), struct gemini_reset, rcdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static unsigned long gemini_pci_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct clk_gemini_pci *pciclk = to_pciclk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) regmap_read(pciclk->map, GEMINI_GLOBAL_MISC_CONTROL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (val & PCI_CLK_66MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return 66000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return 33000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static long gemini_pci_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* We support 33 and 66 MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (rate < 48000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return 33000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return 66000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int gemini_pci_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct clk_gemini_pci *pciclk = to_pciclk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (rate == 33000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return regmap_update_bits(pciclk->map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) GEMINI_GLOBAL_MISC_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PCI_CLK_66MHZ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (rate == 66000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return regmap_update_bits(pciclk->map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) GEMINI_GLOBAL_MISC_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 0, PCI_CLK_66MHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int gemini_pci_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct clk_gemini_pci *pciclk = to_pciclk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) regmap_update_bits(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 0, PCI_CLKRUN_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static void gemini_pci_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct clk_gemini_pci *pciclk = to_pciclk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) regmap_update_bits(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PCI_CLKRUN_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int gemini_pci_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct clk_gemini_pci *pciclk = to_pciclk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) regmap_read(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return !!(val & PCI_CLKRUN_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const struct clk_ops gemini_pci_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .recalc_rate = gemini_pci_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .round_rate = gemini_pci_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .set_rate = gemini_pci_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .enable = gemini_pci_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .disable = gemini_pci_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .is_enabled = gemini_pci_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static struct clk_hw *gemini_pci_clk_setup(const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct regmap *map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct clk_gemini_pci *pciclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) pciclk = kzalloc(sizeof(*pciclk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (!pciclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) init.ops = &gemini_pci_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pciclk->map = map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) pciclk->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ret = clk_hw_register(NULL, &pciclk->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) kfree(pciclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return &pciclk->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * This is a self-deasserting reset controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int gemini_reset(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct gemini_reset *gr = to_gemini_reset(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Manual says to always set BIT 30 (CPU1) to 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return regmap_write(gr->map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) GEMINI_GLOBAL_SOFT_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) BIT(GEMINI_RESET_CPU1) | BIT(id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static int gemini_reset_assert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int gemini_reset_deassert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static int gemini_reset_status(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct gemini_reset *gr = to_gemini_reset(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ret = regmap_read(gr->map, GEMINI_GLOBAL_SOFT_RESET, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return !!(val & BIT(id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const struct reset_control_ops gemini_reset_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .reset = gemini_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .assert = gemini_reset_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .deassert = gemini_reset_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .status = gemini_reset_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static int gemini_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Gives the fracions 1x, 1.5x, 1.85x and 2x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned int cpu_ahb_mult[4] = { 1, 3, 24, 2 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned int cpu_ahb_div[4] = { 1, 2, 13, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct gemini_reset *gr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) unsigned int mult, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) gr = devm_kzalloc(dev, sizeof(*gr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (!gr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Remap the system controller for the exclusive register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) map = syscon_node_to_regmap(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (IS_ERR(map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dev_err(dev, "no syscon regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return PTR_ERR(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) gr->map = map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) gr->rcdev.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) gr->rcdev.nr_resets = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) gr->rcdev.ops = &gemini_reset_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) gr->rcdev.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ret = devm_reset_controller_register(dev, &gr->rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) dev_err(dev, "could not register reset controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* RTC clock 32768 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) hw = clk_hw_register_fixed_rate(NULL, "rtc", NULL, 0, 32768);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) gemini_clk_data->hws[GEMINI_CLK_RTC] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* CPU clock derived as a fixed ratio from the AHB clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) regmap_read(map, GEMINI_GLOBAL_STATUS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) val >>= CPU_AHB_RATIO_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) val &= CPU_AHB_RATIO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) hw = clk_hw_register_fixed_factor(NULL, "cpu", "ahb", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) cpu_ahb_mult[val],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) cpu_ahb_div[val]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) gemini_clk_data->hws[GEMINI_CLK_CPU] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* Security clock is 1:1 or 0.75 of APB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) regmap_read(map, GEMINI_GLOBAL_CLOCK_CONTROL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (val & SECURITY_CLK_SEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) mult = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) mult = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) div = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) hw = clk_hw_register_fixed_factor(NULL, "secdiv", "ahb", 0, mult, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * These are the leaf gates, at boot no clocks are gated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) for (i = 0; i < ARRAY_SIZE(gemini_gates); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) const struct gemini_gate_data *gd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) gd = &gemini_gates[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) gemini_clk_data->hws[GEMINI_CLK_GATES + i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) clk_hw_register_gate(NULL, gd->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) gd->parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) gd->flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) base + GEMINI_GLOBAL_CLOCK_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) gd->bit_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) CLK_GATE_SET_TO_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) &gemini_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * The TV Interface Controller has a 5-bit half divider register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * This clock is supposed to be 27MHz as this is an exact multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * of PAL and NTSC frequencies. The register is undocumented :(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * FIXME: figure out the parent and how the divider works.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) mult = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) div = ((val >> TVC_HALFDIV_SHIFT) & TVC_HALFDIV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) dev_dbg(dev, "TVC half divider value = %d\n", div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) div += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) hw = clk_hw_register_fixed_rate(NULL, "tvcdiv", "xtal", 0, 27000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) gemini_clk_data->hws[GEMINI_CLK_TVC] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* FIXME: very unclear what the parent is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) hw = gemini_pci_clk_setup("PCI", "xtal", map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) gemini_clk_data->hws[GEMINI_CLK_PCI] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* FIXME: very unclear what the parent is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) hw = clk_hw_register_fixed_rate(NULL, "uart", "xtal", 0, 48000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) gemini_clk_data->hws[GEMINI_CLK_UART] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static const struct of_device_id gemini_clk_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) { .compatible = "cortina,gemini-syscon", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static struct platform_driver gemini_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .probe = gemini_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .name = "gemini-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .of_match_table = gemini_clk_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) builtin_platform_driver(gemini_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static void __init gemini_cc_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) unsigned long freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) unsigned int mult, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) gemini_clk_data = kzalloc(struct_size(gemini_clk_data, hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) GEMINI_NUM_CLKS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (!gemini_clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * This way all clock fetched before the platform device probes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * except those we assign here for early use, will be deferred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) for (i = 0; i < GEMINI_NUM_CLKS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) gemini_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) map = syscon_node_to_regmap(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (IS_ERR(map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) pr_err("no syscon regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * We check that the regmap works on this very first access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * but as this is an MMIO-backed regmap, subsequent regmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * access is not going to fail and we skip error checks from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * this point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ret = regmap_read(map, GEMINI_GLOBAL_STATUS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) pr_err("failed to read global status register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * XTAL is the crystal oscillator, 60 or 30 MHz selected from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * strap pin E6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (val & PLL_OSC_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) freq = 30000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) freq = 60000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) hw = clk_hw_register_fixed_rate(NULL, "xtal", NULL, 0, freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) pr_debug("main crystal @%lu MHz\n", freq / 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* VCO clock derived from the crystal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) mult = 13 + ((val >> AHBSPEED_SHIFT) & AHBSPEED_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) div = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* If we run on 30 MHz crystal we have to multiply with two */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (val & PLL_OSC_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) mult *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) hw = clk_hw_register_fixed_factor(NULL, "vco", "xtal", 0, mult, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* The AHB clock is always 1/3 of the VCO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) hw = clk_hw_register_fixed_factor(NULL, "ahb", "vco", 0, 1, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) gemini_clk_data->hws[GEMINI_CLK_AHB] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* The APB clock is always 1/6 of the AHB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) hw = clk_hw_register_fixed_factor(NULL, "apb", "ahb", 0, 1, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) gemini_clk_data->hws[GEMINI_CLK_APB] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* Register the clocks to be accessed by the device tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) gemini_clk_data->num = GEMINI_NUM_CLKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) of_clk_add_hw_provider(np, of_clk_hw_onecell_get, gemini_clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) CLK_OF_DECLARE_DRIVER(gemini_cc, "cortina,gemini-syscon", gemini_cc_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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