^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Gated clock implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static bool clk_always_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) module_param_named(always_on, clk_always_on, bool, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) MODULE_PARM_DESC(always_on, "Always keep clks on except for system suspend.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * DOC: basic gatable clock which can gate and ungate it's ouput
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Traits of this clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * prepare - clk_(un)prepare only ensures parent is (un)prepared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * enable - clk_enable and clk_disable are functional & control gating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * rate - inherits rate from parent. No clk_set_rate support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * parent - fixed parent. No clk_set_parent support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static inline u32 clk_gate_readl(struct clk_gate *gate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) if (gate->flags & CLK_GATE_BIG_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) return ioread32be(gate->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) return readl(gate->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static inline void clk_gate_writel(struct clk_gate *gate, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if (gate->flags & CLK_GATE_BIG_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) iowrite32be(val, gate->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) writel(val, gate->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * It works on following logic:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * For enabling clock, enable = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * set2dis = 1 -> clear bit -> set = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * set2dis = 0 -> set bit -> set = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * For disabling clock, enable = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * set2dis = 1 -> set bit -> set = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * set2dis = 0 -> clear bit -> set = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * So, result is always: enable xor set2dis.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static void clk_gate_endisable(struct clk_hw *hw, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct clk_gate *gate = to_clk_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (clk_always_on && !enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) set ^= enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (gate->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) spin_lock_irqsave(gate->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) __acquire(gate->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (gate->flags & CLK_GATE_HIWORD_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) reg = BIT(gate->bit_idx + 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) reg |= BIT(gate->bit_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) reg = clk_gate_readl(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) reg |= BIT(gate->bit_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) reg &= ~BIT(gate->bit_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) clk_gate_writel(gate, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (gate->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) spin_unlock_irqrestore(gate->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) __release(gate->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int clk_gate_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) clk_gate_endisable(hw, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static void clk_gate_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) clk_gate_endisable(hw, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) int clk_gate_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct clk_gate *gate = to_clk_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) reg = clk_gate_readl(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* if a set bit disables this clk, flip it before masking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (gate->flags & CLK_GATE_SET_TO_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) reg ^= BIT(gate->bit_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) reg &= BIT(gate->bit_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return reg ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) EXPORT_SYMBOL_GPL(clk_gate_is_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) const struct clk_ops clk_gate_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .enable = clk_gate_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .disable = clk_gate_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .is_enabled = clk_gate_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) EXPORT_SYMBOL_GPL(clk_gate_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct clk_hw *__clk_hw_register_gate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct device_node *np, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) const char *parent_name, const struct clk_hw *parent_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) const struct clk_parent_data *parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) void __iomem *reg, u8 bit_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u8 clk_gate_flags, spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct clk_gate *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct clk_init_data init = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (bit_idx > 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) pr_err("gate bit exceeds LOWORD field\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* allocate the gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) gate = kzalloc(sizeof(*gate), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (!gate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) init.ops = &clk_gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) init.parent_names = parent_name ? &parent_name : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) init.parent_hws = parent_hw ? &parent_hw : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) init.parent_data = parent_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (parent_name || parent_hw || parent_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) init.num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* struct clk_gate assignments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) gate->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) gate->bit_idx = bit_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) gate->flags = clk_gate_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) gate->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) gate->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) hw = &gate->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (dev || !np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ret = clk_hw_register(dev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) else if (np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ret = of_clk_hw_register(np, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) kfree(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) EXPORT_SYMBOL_GPL(__clk_hw_register_gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct clk *clk_register_gate(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) const char *parent_name, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) void __iomem *reg, u8 bit_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u8 clk_gate_flags, spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) hw = clk_hw_register_gate(dev, name, parent_name, flags, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) bit_idx, clk_gate_flags, lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return ERR_CAST(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return hw->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) EXPORT_SYMBOL_GPL(clk_register_gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) void clk_unregister_gate(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct clk_gate *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) hw = __clk_get_hw(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (!hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) gate = to_clk_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) clk_unregister(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) kfree(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) EXPORT_SYMBOL_GPL(clk_unregister_gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) void clk_hw_unregister_gate(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct clk_gate *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) gate = to_clk_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) clk_hw_unregister(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) kfree(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) EXPORT_SYMBOL_GPL(clk_hw_unregister_gate);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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