^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Freescale SAI BCLK as a generic clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2020 Michael Walle <michael@walle.cc>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define I2S_CSR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define I2S_CR2 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CSR_BCE_BIT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CR2_BCD BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CR2_DIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CR2_DIV_WIDTH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct fsl_sai_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct clk_divider div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct clk_gate gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static int fsl_sai_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct fsl_sai_clk *sai_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct clk_parent_data pdata = { .index = 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) sai_clk = devm_kzalloc(dev, sizeof(*sai_clk), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) if (!sai_clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) spin_lock_init(&sai_clk->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) sai_clk->gate.reg = base + I2S_CSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) sai_clk->gate.bit_idx = CSR_BCE_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) sai_clk->gate.lock = &sai_clk->lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) sai_clk->div.reg = base + I2S_CR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) sai_clk->div.shift = CR2_DIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) sai_clk->div.width = CR2_DIV_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) sai_clk->div.lock = &sai_clk->lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* set clock direction, we are the BCLK master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) writel(CR2_BCD, base + I2S_CR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) hw = clk_hw_register_composite_pdata(dev, dev->of_node->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) &pdata, 1, NULL, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) &sai_clk->div.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) &clk_divider_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) &sai_clk->gate.hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) &clk_gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) CLK_SET_RATE_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) platform_set_drvdata(pdev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int fsl_sai_clk_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct clk_hw *hw = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) clk_hw_unregister_composite(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const struct of_device_id of_fsl_sai_clk_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { .compatible = "fsl,vf610-sai-clock" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MODULE_DEVICE_TABLE(of, of_fsl_sai_clk_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static struct platform_driver fsl_sai_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .probe = fsl_sai_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .remove = fsl_sai_clk_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .name = "fsl-sai-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .of_match_table = of_fsl_sai_clk_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) module_platform_driver(fsl_sai_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MODULE_DESCRIPTION("Freescale SAI bitclock-as-a-clock driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MODULE_AUTHOR("Michael Walle <michael@walle.cc>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MODULE_ALIAS("platform:fsl-sai-clk");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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