^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Fixed rate clock implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * DOC: basic fixed-rate clock that cannot gate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Traits of this clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * prepare - clk_(un)prepare only ensures parents are prepared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * enable - clk_enable only ensures parents are enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * rate - rate is always a fixed value. No clk_set_rate support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * parent - fixed parent. No clk_set_parent support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static unsigned long clk_fixed_rate_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) return to_clk_fixed_rate(hw)->fixed_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static unsigned long clk_fixed_rate_recalc_accuracy(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) unsigned long parent_accuracy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct clk_fixed_rate *fixed = to_clk_fixed_rate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if (fixed->flags & CLK_FIXED_RATE_PARENT_ACCURACY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return parent_accuracy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return fixed->fixed_accuracy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) const struct clk_ops clk_fixed_rate_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .recalc_rate = clk_fixed_rate_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .recalc_accuracy = clk_fixed_rate_recalc_accuracy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) EXPORT_SYMBOL_GPL(clk_fixed_rate_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct device_node *np, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) const char *parent_name, const struct clk_hw *parent_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) const struct clk_parent_data *parent_data, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned long fixed_rate, unsigned long fixed_accuracy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned long clk_fixed_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct clk_fixed_rate *fixed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct clk_init_data init = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* allocate fixed-rate clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (!fixed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) init.ops = &clk_fixed_rate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) init.parent_names = parent_name ? &parent_name : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) init.parent_hws = parent_hw ? &parent_hw : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) init.parent_data = parent_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (parent_name || parent_hw || parent_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) init.num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* struct clk_fixed_rate assignments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) fixed->flags = clk_fixed_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) fixed->fixed_rate = fixed_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) fixed->fixed_accuracy = fixed_accuracy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) fixed->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* register the clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) hw = &fixed->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (dev || !np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ret = clk_hw_register(dev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) else if (np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ret = of_clk_hw_register(np, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) kfree(fixed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) EXPORT_SYMBOL_GPL(__clk_hw_register_fixed_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) const char *parent_name, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned long fixed_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) hw = clk_hw_register_fixed_rate_with_accuracy(dev, name, parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) flags, fixed_rate, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return ERR_CAST(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return hw->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) EXPORT_SYMBOL_GPL(clk_register_fixed_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) void clk_unregister_fixed_rate(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) hw = __clk_get_hw(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (!hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) clk_unregister(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) kfree(to_clk_fixed_rate(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) EXPORT_SYMBOL_GPL(clk_unregister_fixed_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) void clk_hw_unregister_fixed_rate(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct clk_fixed_rate *fixed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) fixed = to_clk_fixed_rate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) clk_hw_unregister(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) kfree(fixed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) EXPORT_SYMBOL_GPL(clk_hw_unregister_fixed_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static struct clk_hw *_of_fixed_clk_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) const char *clk_name = node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 accuracy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (of_property_read_u32(node, "clock-frequency", &rate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return ERR_PTR(-EIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) of_property_read_u32(node, "clock-accuracy", &accuracy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) of_property_read_string(node, "clock-output-names", &clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) hw = clk_hw_register_fixed_rate_with_accuracy(NULL, clk_name, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 0, rate, accuracy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) clk_hw_unregister_fixed_rate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * of_fixed_clk_setup() - Setup function for simple fixed rate clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * @node: device node for the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) void __init of_fixed_clk_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) _of_fixed_clk_setup(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) CLK_OF_DECLARE(fixed_clk, "fixed-clock", of_fixed_clk_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int of_fixed_clk_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct clk_hw *hw = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) of_clk_del_provider(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) clk_hw_unregister_fixed_rate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int of_fixed_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * This function is not executed when of_fixed_clk_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * succeeded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) hw = _of_fixed_clk_setup(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) platform_set_drvdata(pdev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static const struct of_device_id of_fixed_clk_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { .compatible = "fixed-clock" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static struct platform_driver of_fixed_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .name = "of_fixed_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .of_match_table = of_fixed_clk_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .probe = of_fixed_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .remove = of_fixed_clk_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) builtin_platform_driver(of_fixed_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags