Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * DOC: basic fixed multiplier and divider clock that cannot gate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * Traits of this clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * prepare - clk_prepare only ensures that parents are prepared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * enable - clk_enable only ensures that parents are enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * rate - rate is fixed.  clk->rate = parent->rate / div * mult
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * parent - fixed parent.  No clk_set_parent support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 		unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	unsigned long long int rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	rate = (unsigned long long int)parent_rate * fix->mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	do_div(rate, fix->div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	return (unsigned long)rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) static long clk_factor_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 				unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		unsigned long best_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		best_parent = (rate / fix->mult) * fix->div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		*prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	return (*prate / fix->div) * fix->mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static int clk_factor_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 				unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	 * We must report success but we can do so unconditionally because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	 * clk_factor_round_rate returns values that ensure this call is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	 * nop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) const struct clk_ops clk_fixed_factor_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	.round_rate = clk_factor_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	.set_rate = clk_factor_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	.recalc_rate = clk_factor_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) EXPORT_SYMBOL_GPL(clk_fixed_factor_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static struct clk_hw *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		const char *name, const char *parent_name, int index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		unsigned long flags, unsigned int mult, unsigned int div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	struct clk_fixed_factor *fix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	struct clk_init_data init = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct clk_parent_data pdata = { .index = index };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	fix = kmalloc(sizeof(*fix), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	if (!fix)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	/* struct clk_fixed_factor assignments */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	fix->mult = mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	fix->div = div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	fix->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	init.ops = &clk_fixed_factor_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	if (parent_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		init.parent_data = &pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	hw = &fix->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	if (dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		ret = clk_hw_register(dev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		ret = of_clk_hw_register(np, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		kfree(fix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		const char *name, const char *parent_name, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		unsigned int mult, unsigned int div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 					      flags, mult, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		const char *parent_name, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		unsigned int mult, unsigned int div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	hw = clk_hw_register_fixed_factor(dev, name, parent_name, flags, mult,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 					  div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		return ERR_CAST(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	return hw->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) EXPORT_SYMBOL_GPL(clk_register_fixed_factor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) void clk_unregister_fixed_factor(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	hw = __clk_get_hw(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (!hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	clk_unregister(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	kfree(to_clk_fixed_factor(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) EXPORT_SYMBOL_GPL(clk_unregister_fixed_factor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) void clk_hw_unregister_fixed_factor(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	struct clk_fixed_factor *fix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	fix = to_clk_fixed_factor(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	clk_hw_unregister(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	kfree(fix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) EXPORT_SYMBOL_GPL(clk_hw_unregister_fixed_factor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const struct of_device_id set_rate_parent_matches[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	{ .compatible = "allwinner,sun4i-a10-pll3-2x-clk" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	{ /* Sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	const char *clk_name = node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	u32 div, mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	if (of_property_read_u32(node, "clock-div", &div)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		pr_err("%s Fixed factor clock <%pOFn> must have a clock-div property\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			__func__, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		return ERR_PTR(-EIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	if (of_property_read_u32(node, "clock-mult", &mult)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		pr_err("%s Fixed factor clock <%pOFn> must have a clock-mult property\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 			__func__, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		return ERR_PTR(-EIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	of_property_read_string(node, "clock-output-names", &clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	if (of_match_node(set_rate_parent_matches, node))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		flags |= CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 					    flags, mult, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (IS_ERR(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		 * Clear OF_POPULATED flag so that clock registration can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		 * attempted again from probe function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		of_node_clear_flag(node, OF_POPULATED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		return ERR_CAST(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		clk_hw_unregister_fixed_factor(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)  * of_fixed_factor_clk_setup() - Setup function for simple fixed factor clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)  * @node:	device node for the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) void __init of_fixed_factor_clk_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	_of_fixed_factor_clk_setup(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) CLK_OF_DECLARE(fixed_factor_clk, "fixed-factor-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		of_fixed_factor_clk_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int of_fixed_factor_clk_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	struct clk_hw *clk = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	of_clk_del_provider(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	clk_hw_unregister_fixed_factor(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static int of_fixed_factor_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	struct clk_hw *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	 * This function is not executed when of_fixed_factor_clk_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	 * succeeded.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	clk = _of_fixed_factor_clk_setup(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	if (IS_ERR(clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	platform_set_drvdata(pdev, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static const struct of_device_id of_fixed_factor_clk_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	{ .compatible = "fixed-factor-clock" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MODULE_DEVICE_TABLE(of, of_fixed_factor_clk_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static struct platform_driver of_fixed_factor_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		.name = "of_fixed_factor_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		.of_match_table = of_fixed_factor_clk_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	.probe = of_fixed_factor_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	.remove = of_fixed_factor_clk_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) builtin_platform_driver(of_fixed_factor_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #endif