^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2014 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Sylwester Nawrocki <s.nawrocki@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk/clk-conf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/printk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) static int __set_clk_parents(struct device_node *node, bool clk_supplier)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct of_phandle_args clkspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) int index, rc, num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct clk *clk, *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) num_parents = of_count_phandle_with_args(node, "assigned-clock-parents",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) "#clock-cells");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) if (num_parents == -EINVAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) pr_err("clk: invalid value of clock-parents property at %pOF\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) for (index = 0; index < num_parents; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) rc = of_parse_phandle_with_args(node, "assigned-clock-parents",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) "#clock-cells", index, &clkspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* skip empty (null) phandles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) if (rc == -ENOENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) if (clkspec.np == node && !clk_supplier)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) pclk = of_clk_get_from_provider(&clkspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) if (IS_ERR(pclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if (PTR_ERR(pclk) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) pr_warn("clk: couldn't get parent clock %d for %pOF\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) index, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return PTR_ERR(pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) rc = of_parse_phandle_with_args(node, "assigned-clocks",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) "#clock-cells", index, &clkspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (clkspec.np == node && !clk_supplier) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) clk = of_clk_get_from_provider(&clkspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (PTR_ERR(clk) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) pr_warn("clk: couldn't get assigned clock %d for %pOF\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) index, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) rc = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) rc = clk_set_parent(clk, pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) pr_err("clk: failed to reparent %s to %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __clk_get_name(clk), __clk_get_name(pclk), rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) clk_put(pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) clk_put(pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int __set_clk_rates(struct device_node *node, bool clk_supplier)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct of_phandle_args clkspec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) const __be32 *cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int rc, index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) of_property_for_each_u32(node, "assigned-clock-rates", prop, cur, rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) rc = of_parse_phandle_with_args(node, "assigned-clocks",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "#clock-cells", index, &clkspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* skip empty (null) phandles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (rc == -ENOENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (clkspec.np == node && !clk_supplier)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) clk = of_clk_get_from_provider(&clkspec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (PTR_ERR(clk) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) pr_warn("clk: couldn't get clock %d for %pOF\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) index, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) rc = clk_set_rate(clk, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) pr_err("clk: couldn't set %s clk rate to %u (%d), current rate: %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) __clk_get_name(clk), rate, rc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) clk_get_rate(clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * of_clk_set_defaults() - parse and set assigned clocks configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * @node: device node to apply clock settings for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * @clk_supplier: true if clocks supplied by @node should also be considered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * This function parses 'assigned-{clocks/clock-parents/clock-rates}' properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * and sets any specified clock parents and rates. The @clk_supplier argument
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * should be set to true if @node may be also a clock supplier of any clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * listed in its 'assigned-clocks' or 'assigned-clock-parents' properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * If @clk_supplier is false the function exits returning 0 as soon as it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * determines the @node is also a supplier of any of the clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int of_clk_set_defaults(struct device_node *node, bool clk_supplier)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (!node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) rc = __set_clk_parents(node, clk_supplier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return __set_clk_rates(node, clk_supplier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) EXPORT_SYMBOL_GPL(of_clk_set_defaults);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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