Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2013 NVIDIA CORPORATION.  All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) static u8 clk_composite_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 	struct clk_composite *composite = to_clk_composite(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 	const struct clk_ops *mux_ops = composite->mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 	struct clk_hw *mux_hw = composite->mux_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	__clk_hw_set_clk(mux_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	return mux_ops->get_parent(mux_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	struct clk_composite *composite = to_clk_composite(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	const struct clk_ops *mux_ops = composite->mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	struct clk_hw *mux_hw = composite->mux_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	__clk_hw_set_clk(mux_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	return mux_ops->set_parent(mux_hw, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 					    unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct clk_composite *composite = to_clk_composite(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	const struct clk_ops *rate_ops = composite->rate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct clk_hw *rate_hw = composite->rate_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	__clk_hw_set_clk(rate_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	return rate_ops->recalc_rate(rate_hw, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static int clk_composite_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 					struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	struct clk_composite *composite = to_clk_composite(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	const struct clk_ops *rate_ops = composite->rate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	const struct clk_ops *mux_ops = composite->mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	struct clk_hw *rate_hw = composite->rate_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct clk_hw *mux_hw = composite->mux_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct clk_hw *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	unsigned long parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	long tmp_rate, best_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	unsigned long rate_diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	unsigned long best_rate_diff = ULONG_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	if (rate_hw && rate_ops && rate_ops->determine_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		__clk_hw_set_clk(rate_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		return rate_ops->determine_rate(rate_hw, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	} else if (rate_hw && rate_ops && rate_ops->round_rate &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		   mux_hw && mux_ops && mux_ops->set_parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		req->best_parent_hw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 			parent = clk_hw_get_parent(mux_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 			req->best_parent_hw = parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 			req->best_parent_rate = clk_hw_get_rate(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 			rate = rate_ops->round_rate(rate_hw, req->rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 						    &req->best_parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 			if (rate < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 				return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 			req->rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 			return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		for (i = 0; i < clk_hw_get_num_parents(mux_hw); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 			parent = clk_hw_get_parent_by_index(mux_hw, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			if (!parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 			parent_rate = clk_hw_get_rate(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			tmp_rate = rate_ops->round_rate(rate_hw, req->rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 							&parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			if (tmp_rate < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 			rate_diff = abs(req->rate - tmp_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 			if (!rate_diff || !req->best_parent_hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 				       || best_rate_diff > rate_diff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 				req->best_parent_hw = parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 				req->best_parent_rate = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 				best_rate_diff = rate_diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 				best_rate = tmp_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 			if (!rate_diff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 				return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		req->rate = best_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	} else if (mux_hw && mux_ops && mux_ops->determine_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		__clk_hw_set_clk(mux_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		return mux_ops->determine_rate(mux_hw, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		pr_err("clk: clk_composite_determine_rate function called, but no mux or rate callback set!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 				  unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	struct clk_composite *composite = to_clk_composite(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	const struct clk_ops *rate_ops = composite->rate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	struct clk_hw *rate_hw = composite->rate_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	__clk_hw_set_clk(rate_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	return rate_ops->round_rate(rate_hw, rate, prate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			       unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	struct clk_composite *composite = to_clk_composite(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	const struct clk_ops *rate_ops = composite->rate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	struct clk_hw *rate_hw = composite->rate_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	__clk_hw_set_clk(rate_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	return rate_ops->set_rate(rate_hw, rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int clk_composite_set_rate_and_parent(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 					     unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 					     unsigned long parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 					     u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	struct clk_composite *composite = to_clk_composite(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	const struct clk_ops *rate_ops = composite->rate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	const struct clk_ops *mux_ops = composite->mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	struct clk_hw *rate_hw = composite->rate_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	struct clk_hw *mux_hw = composite->mux_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	unsigned long temp_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	__clk_hw_set_clk(rate_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	__clk_hw_set_clk(mux_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	temp_rate = rate_ops->recalc_rate(rate_hw, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (temp_rate > rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		rate_ops->set_rate(rate_hw, rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		mux_ops->set_parent(mux_hw, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		mux_ops->set_parent(mux_hw, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		rate_ops->set_rate(rate_hw, rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int clk_composite_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	struct clk_composite *composite = to_clk_composite(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	const struct clk_ops *gate_ops = composite->gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct clk_hw *gate_hw = composite->gate_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	__clk_hw_set_clk(gate_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	return gate_ops->is_enabled(gate_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int clk_composite_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	struct clk_composite *composite = to_clk_composite(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	const struct clk_ops *gate_ops = composite->gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	struct clk_hw *gate_hw = composite->gate_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	__clk_hw_set_clk(gate_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	return gate_ops->enable(gate_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static void clk_composite_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	struct clk_composite *composite = to_clk_composite(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	const struct clk_ops *gate_ops = composite->gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct clk_hw *gate_hw = composite->gate_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	__clk_hw_set_clk(gate_hw, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	gate_ops->disable(gate_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static struct clk_hw *__clk_hw_register_composite(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			const char *name, const char * const *parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			const struct clk_parent_data *pdata, int num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	struct clk_init_data init = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	struct clk_composite *composite;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	struct clk_ops *clk_composite_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	composite = kzalloc(sizeof(*composite), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	if (!composite)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (parent_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		init.parent_data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	init.num_parents = num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	hw = &composite->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	clk_composite_ops = &composite->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	if (mux_hw && mux_ops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		if (!mux_ops->get_parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			hw = ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		composite->mux_hw = mux_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		composite->mux_ops = mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		clk_composite_ops->get_parent = clk_composite_get_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		if (mux_ops->set_parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			clk_composite_ops->set_parent = clk_composite_set_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		if (mux_ops->determine_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			clk_composite_ops->determine_rate = clk_composite_determine_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	if (rate_hw && rate_ops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		if (!rate_ops->recalc_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			hw = ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		clk_composite_ops->recalc_rate = clk_composite_recalc_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		if (rate_ops->determine_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			clk_composite_ops->determine_rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 				clk_composite_determine_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		else if (rate_ops->round_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			clk_composite_ops->round_rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 				clk_composite_round_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		/* .set_rate requires either .round_rate or .determine_rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		if (rate_ops->set_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 			if (rate_ops->determine_rate || rate_ops->round_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 				clk_composite_ops->set_rate =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 						clk_composite_set_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 				WARN(1, "%s: missing round_rate op is required\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 						__func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		composite->rate_hw = rate_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		composite->rate_ops = rate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	if (mux_hw && mux_ops && rate_hw && rate_ops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		if (mux_ops->set_parent && rate_ops->set_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 			clk_composite_ops->set_rate_and_parent =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			clk_composite_set_rate_and_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	if (gate_hw && gate_ops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		if (!gate_ops->is_enabled || !gate_ops->enable ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		    !gate_ops->disable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 			hw = ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 			goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		composite->gate_hw = gate_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		composite->gate_ops = gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		clk_composite_ops->is_enabled = clk_composite_is_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		clk_composite_ops->enable = clk_composite_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		clk_composite_ops->disable = clk_composite_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	init.ops = clk_composite_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	composite->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	ret = clk_hw_register(dev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	if (composite->mux_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		composite->mux_hw->clk = hw->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	if (composite->rate_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		composite->rate_hw->clk = hw->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	if (composite->gate_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		composite->gate_hw->clk = hw->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	kfree(composite);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 			const char * const *parent_names, int num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 			struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 			struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 			struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 			unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	return __clk_hw_register_composite(dev, name, parent_names, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 					   num_parents, mux_hw, mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 					   rate_hw, rate_ops, gate_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 					   gate_ops, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) EXPORT_SYMBOL_GPL(clk_hw_register_composite);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 			const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 			const struct clk_parent_data *parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 			int num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 			struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 			struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 			unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	return __clk_hw_register_composite(dev, name, NULL, parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 					   num_parents, mux_hw, mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 					   rate_hw, rate_ops, gate_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 					   gate_ops, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct clk *clk_register_composite(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 			const char * const *parent_names, int num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 			struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 			struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 			struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 			unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	hw = clk_hw_register_composite(dev, name, parent_names, num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 			mux_hw, mux_ops, rate_hw, rate_ops, gate_hw, gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 			flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		return ERR_CAST(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	return hw->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) EXPORT_SYMBOL_GPL(clk_register_composite);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 			const struct clk_parent_data *parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 			int num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 			struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 			struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 			struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 			unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	hw = clk_hw_register_composite_pdata(dev, name, parent_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 			num_parents, mux_hw, mux_ops, rate_hw, rate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 			gate_hw, gate_ops, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		return ERR_CAST(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	return hw->clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) void clk_unregister_composite(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	struct clk_composite *composite;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	hw = __clk_get_hw(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	if (!hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	composite = to_clk_composite(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	clk_unregister(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	kfree(composite);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) void clk_hw_unregister_composite(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	struct clk_composite *composite;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	composite = to_clk_composite(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	clk_hw_unregister(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	kfree(composite);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) EXPORT_SYMBOL_GPL(clk_hw_unregister_composite);