^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Cirrus Logic CLPS711X CLK driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mfd/syscon/clps711x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <dt-bindings/clock/clps711x-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLPS711X_SYSCON1 (0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLPS711X_SYSCON2 (0x1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLPS711X_SYSFLG2 (CLPS711X_SYSCON2 + SYSFLG_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLPS711X_PLLR (0xa5a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLPS711X_EXT_FREQ (13000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLPS711X_OSC_FREQ (3686400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static const struct clk_div_table spi_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) { .val = 0, .div = 32, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) { .val = 1, .div = 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) { .val = 2, .div = 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) { .val = 3, .div = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static const struct clk_div_table timer_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { .val = 0, .div = 256, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) { .val = 1, .div = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct clps711x_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct clk_hw_onecell_data clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static void __init clps711x_clk_init_dt(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 tmp, f_cpu, f_pll, f_bus, f_tim, f_pwm, f_spi, fref = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct clps711x_clk *clps711x_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) WARN_ON(of_property_read_u32(np, "startup-frequency", &fref));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) BUG_ON(!base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) clps711x_clk = kzalloc(struct_size(clps711x_clk, clk_data.hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) CLPS711X_CLK_MAX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) BUG_ON(!clps711x_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) spin_lock_init(&clps711x_clk->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Read PLL multiplier value and sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) tmp = readl(base + CLPS711X_PLLR) >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (((tmp >= 10) && (tmp <= 50)) || !fref)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) f_pll = DIV_ROUND_UP(CLPS711X_OSC_FREQ * tmp, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) f_pll = fref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) tmp = readl(base + CLPS711X_SYSFLG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (tmp & SYSFLG2_CKMODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) f_cpu = CLPS711X_EXT_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) f_bus = CLPS711X_EXT_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) f_spi = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) f_pll = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) f_pwm = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) f_cpu = f_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (f_cpu > 36864000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) f_bus = DIV_ROUND_UP(f_cpu, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) f_bus = 36864000 / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) f_spi = DIV_ROUND_CLOSEST(f_cpu, 576);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) f_pwm = DIV_ROUND_CLOSEST(f_cpu, 768);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (tmp & SYSFLG2_CKMODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (readl(base + CLPS711X_SYSCON2) & SYSCON2_OSTB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) f_tim = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) f_tim = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) f_tim = DIV_ROUND_CLOSEST(f_cpu, 144);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) tmp = readl(base + CLPS711X_SYSCON1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Timer1 in free running mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * Counter will wrap around to 0xffff when it underflows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * and will continue to count down.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) tmp &= ~(SYSCON1_TC1M | SYSCON1_TC1S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Timer2 in prescale mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * Value writen is automatically re-loaded when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * the counter underflows.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) tmp |= SYSCON1_TC2M | SYSCON1_TC2S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) writel(tmp, base + CLPS711X_SYSCON1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) clps711x_clk->clk_data.hws[CLPS711X_CLK_DUMMY] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) clk_hw_register_fixed_rate(NULL, "dummy", NULL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) clps711x_clk->clk_data.hws[CLPS711X_CLK_CPU] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) clk_hw_register_fixed_rate(NULL, "cpu", NULL, 0, f_cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) clps711x_clk->clk_data.hws[CLPS711X_CLK_BUS] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) clk_hw_register_fixed_rate(NULL, "bus", NULL, 0, f_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) clps711x_clk->clk_data.hws[CLPS711X_CLK_PLL] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) clk_hw_register_fixed_rate(NULL, "pll", NULL, 0, f_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMERREF] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) clk_hw_register_fixed_rate(NULL, "timer_ref", NULL, 0, f_tim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) clk_hw_register_divider_table(NULL, "timer1", "timer_ref", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) base + CLPS711X_SYSCON1, 5, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) timer_div_table, &clps711x_clk->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER2] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) clk_hw_register_divider_table(NULL, "timer2", "timer_ref", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) base + CLPS711X_SYSCON1, 7, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) timer_div_table, &clps711x_clk->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) clps711x_clk->clk_data.hws[CLPS711X_CLK_PWM] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) clk_hw_register_fixed_rate(NULL, "pwm", NULL, 0, f_pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) clps711x_clk->clk_data.hws[CLPS711X_CLK_SPIREF] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) clk_hw_register_fixed_rate(NULL, "spi_ref", NULL, 0, f_spi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) clps711x_clk->clk_data.hws[CLPS711X_CLK_SPI] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) clk_hw_register_divider_table(NULL, "spi", "spi_ref", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) base + CLPS711X_SYSCON1, 16, 2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) spi_div_table, &clps711x_clk->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) clps711x_clk->clk_data.hws[CLPS711X_CLK_UART] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) clk_hw_register_fixed_factor(NULL, "uart", "bus", 0, 1, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) clps711x_clk->clk_data.hws[CLPS711X_CLK_TICK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) clk_hw_register_fixed_rate(NULL, "tick", NULL, 0, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) for (tmp = 0; tmp < CLPS711X_CLK_MAX; tmp++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (IS_ERR(clps711x_clk->clk_data.hws[tmp]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) pr_err("clk %i: register failed with %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) tmp, PTR_ERR(clps711x_clk->clk_data.hws[tmp]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) clps711x_clk->clk_data.num = CLPS711X_CLK_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) &clps711x_clk->clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) CLK_OF_DECLARE(clps711x, "cirrus,ep7209-clk", clps711x_clk_init_dt);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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