^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Driver for TI Multi PLL CDCE913/925/937/949 clock synthesizer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This driver always connects the Y1 to the input clock, Y2/Y3 to PLL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Y4/Y5 to PLL2, and so on. PLL frequency is set on a first-come-first-serve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * basis. Clients can directly request any frequency that the chip can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * deliver using the standard clk framework. In addition, the device can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * be configured and activated via the devicetree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2014, Topic Embedded Products
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Licenced under GPL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/gcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Each chip has different number of PLLs and outputs, for example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * The CECE925 has 2 PLLs which can be routed through dividers to 5 outputs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Model this as 2 PLL clocks which are parents to the outputs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) CDCE913,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) CDCE925,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) CDCE937,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) CDCE949,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct clk_cdce925_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int num_plls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int num_outputs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static const struct clk_cdce925_chip_info clk_cdce925_chip_info_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) [CDCE913] = { .num_plls = 1, .num_outputs = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) [CDCE925] = { .num_plls = 2, .num_outputs = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) [CDCE937] = { .num_plls = 3, .num_outputs = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) [CDCE949] = { .num_plls = 4, .num_outputs = 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MAX_NUMBER_OF_PLLS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MAX_NUMBER_OF_OUTPUTS 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CDCE925_REG_GLOBAL1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CDCE925_REG_Y1SPIPDIVH 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CDCE925_REG_PDIVL 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CDCE925_REG_XCSEL 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* PLL parameters start at 0x10, steps of 0x10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CDCE925_OFFSET_PLL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Add CDCE925_OFFSET_PLL * (pll) to these registers before sending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CDCE925_PLL_MUX_OUTPUTS 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CDCE925_PLL_MULDIV 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CDCE925_PLL_FREQUENCY_MIN 80000000ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CDCE925_PLL_FREQUENCY_MAX 230000000ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct clk_cdce925_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct clk_cdce925_output {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct clk_cdce925_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u8 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u16 pdiv; /* 1..127 for Y2-Y9; 1..1023 for Y1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define to_clk_cdce925_output(_hw) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) container_of(_hw, struct clk_cdce925_output, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct clk_cdce925_pll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct clk_cdce925_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u8 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u16 m; /* 1..511 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u16 n; /* 1..4095 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define to_clk_cdce925_pll(_hw) container_of(_hw, struct clk_cdce925_pll, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct clk_cdce925_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct i2c_client *i2c_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) const struct clk_cdce925_chip_info *chip_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct clk_cdce925_pll pll[MAX_NUMBER_OF_PLLS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct clk_cdce925_output clk[MAX_NUMBER_OF_OUTPUTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static unsigned long cdce925_pll_calculate_rate(unsigned long parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u16 n, u16 m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if ((!m || !n) || (m == n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return parent_rate; /* In bypass mode runs at same frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return mult_frac(parent_rate, (unsigned long)n, (unsigned long)m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static unsigned long cdce925_pll_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Output frequency of PLL is Fout = (Fin/Pdiv)*(N/M) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return cdce925_pll_calculate_rate(parent_rate, data->n, data->m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void cdce925_pll_find_rate(unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned long parent_rate, u16 *n, u16 *m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned long un;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned long um;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned long g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (rate <= parent_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Can always deliver parent_rate in bypass mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) rate = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) *n = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) *m = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* In PLL mode, need to apply min/max range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (rate < CDCE925_PLL_FREQUENCY_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) rate = CDCE925_PLL_FREQUENCY_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) else if (rate > CDCE925_PLL_FREQUENCY_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) rate = CDCE925_PLL_FREQUENCY_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) g = gcd(rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) um = parent_rate / g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) un = rate / g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* When outside hw range, reduce to fit (rounding errors) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) while ((un > 4095) || (um > 511)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) un >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) um >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (un == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) un = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (um == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) um = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) *n = un;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) *m = um;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static long cdce925_pll_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u16 n, m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) cdce925_pll_find_rate(rate, *parent_rate, &n, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return (long)cdce925_pll_calculate_rate(*parent_rate, n, m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int cdce925_pll_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (!rate || (rate == parent_rate)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) data->m = 0; /* Bypass mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) data->n = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if ((rate < CDCE925_PLL_FREQUENCY_MIN) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) (rate > CDCE925_PLL_FREQUENCY_MAX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) pr_debug("%s: rate %lu outside PLL range.\n", __func__, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (rate < parent_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) pr_debug("%s: rate %lu less than parent rate %lu.\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) cdce925_pll_find_rate(rate, parent_rate, &data->n, &data->m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* calculate p = max(0, 4 - int(log2 (n/m))) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static u8 cdce925_pll_calc_p(u16 n, u16 m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u8 p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u16 r = n / m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (r >= 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) p = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) while (r > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) r >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) --p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Returns VCO range bits for VCO1_0_RANGE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static u8 cdce925_pll_calc_range_bits(struct clk_hw *hw, u16 n, u16 m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct clk *parent = clk_get_parent(hw->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned long rate = clk_get_rate(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) rate = mult_frac(rate, (unsigned long)n, (unsigned long)m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (rate >= 175000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (rate >= 150000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (rate >= 125000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* I2C clock, hence everything must happen in (un)prepare because this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * may sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int cdce925_pll_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u16 n = data->n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u16 m = data->m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u16 r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u8 q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u8 p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u16 nn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u8 pll[4]; /* Bits are spread out over 4 byte registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u8 reg_ofs = data->index * CDCE925_OFFSET_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if ((!m || !n) || (m == n)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Set PLL mux to bypass mode, leave the rest as is */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) regmap_update_bits(data->chip->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* According to data sheet: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* p = max(0, 4 - int(log2 (n/m))) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) p = cdce925_pll_calc_p(n, m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* nn = n * 2^p */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) nn = n * BIT(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* q = int(nn/m) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) q = nn / m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if ((q < 16) || (q > 63)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) pr_debug("%s invalid q=%d\n", __func__, q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) r = nn - (m*q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (r > 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) pr_debug("%s invalid r=%d\n", __func__, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) pr_debug("%s n=%d m=%d p=%d q=%d r=%d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) n, m, p, q, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* encode into register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) pll[0] = n >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pll[1] = ((n & 0x0F) << 4) | ((r >> 5) & 0x0F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) pll[2] = ((r & 0x1F) << 3) | ((q >> 3) & 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) pll[3] = ((q & 0x07) << 5) | (p << 2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) cdce925_pll_calc_range_bits(hw, n, m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* Write to registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) for (i = 0; i < ARRAY_SIZE(pll); ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) regmap_write(data->chip->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) reg_ofs + CDCE925_PLL_MULDIV + i, pll[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Enable PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) regmap_update_bits(data->chip->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static void cdce925_pll_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u8 reg_ofs = data->index * CDCE925_OFFSET_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) regmap_update_bits(data->chip->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const struct clk_ops cdce925_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .prepare = cdce925_pll_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .unprepare = cdce925_pll_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .recalc_rate = cdce925_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .round_rate = cdce925_pll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .set_rate = cdce925_pll_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static void cdce925_clk_set_pdiv(struct clk_cdce925_output *data, u16 pdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) switch (data->index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) regmap_update_bits(data->chip->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) CDCE925_REG_Y1SPIPDIVH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 0x03, (pdiv >> 8) & 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) regmap_write(data->chip->regmap, 0x03, pdiv & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) regmap_update_bits(data->chip->regmap, 0x16, 0x7F, pdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) regmap_update_bits(data->chip->regmap, 0x17, 0x7F, pdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) regmap_update_bits(data->chip->regmap, 0x26, 0x7F, pdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) regmap_update_bits(data->chip->regmap, 0x27, 0x7F, pdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) regmap_update_bits(data->chip->regmap, 0x36, 0x7F, pdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) regmap_update_bits(data->chip->regmap, 0x37, 0x7F, pdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) regmap_update_bits(data->chip->regmap, 0x46, 0x7F, pdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) regmap_update_bits(data->chip->regmap, 0x47, 0x7F, pdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static void cdce925_clk_activate(struct clk_cdce925_output *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) switch (data->index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) regmap_update_bits(data->chip->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) CDCE925_REG_Y1SPIPDIVH, 0x0c, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) regmap_update_bits(data->chip->regmap, 0x14, 0x03, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) regmap_update_bits(data->chip->regmap, 0x24, 0x03, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) regmap_update_bits(data->chip->regmap, 0x34, 0x03, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) regmap_update_bits(data->chip->regmap, 0x44, 0x03, 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static int cdce925_clk_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct clk_cdce925_output *data = to_clk_cdce925_output(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) cdce925_clk_set_pdiv(data, data->pdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) cdce925_clk_activate(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static void cdce925_clk_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct clk_cdce925_output *data = to_clk_cdce925_output(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* Disable clock by setting divider to "0" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) cdce925_clk_set_pdiv(data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static unsigned long cdce925_clk_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct clk_cdce925_output *data = to_clk_cdce925_output(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (data->pdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return parent_rate / data->pdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static u16 cdce925_calc_divider(unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) unsigned long divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (!rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (rate >= parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) divider = DIV_ROUND_CLOSEST(parent_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (divider > 0x7F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) divider = 0x7F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return (u16)divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static unsigned long cdce925_clk_best_parent_rate(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct clk_hw *hw, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct clk *pll = clk_get_parent(hw->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct clk *root = clk_get_parent(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) unsigned long root_rate = clk_get_rate(root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) unsigned long best_rate_error = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u16 pdiv_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u16 pdiv_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u16 pdiv_best;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u16 pdiv_now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (root_rate % rate == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return root_rate; /* Don't need the PLL, use bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) pdiv_min = (u16)max(1ul, DIV_ROUND_UP(CDCE925_PLL_FREQUENCY_MIN, rate));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) pdiv_max = (u16)min(127ul, CDCE925_PLL_FREQUENCY_MAX / rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (pdiv_min > pdiv_max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return 0; /* No can do? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) pdiv_best = pdiv_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) for (pdiv_now = pdiv_min; pdiv_now < pdiv_max; ++pdiv_now) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) unsigned long target_rate = rate * pdiv_now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) long pll_rate = clk_round_rate(pll, target_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned long actual_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned long rate_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (pll_rate <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) actual_rate = pll_rate / pdiv_now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) rate_error = abs((long)actual_rate - (long)rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (rate_error < best_rate_error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) pdiv_best = pdiv_now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) best_rate_error = rate_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* TODO: Consider PLL frequency based on smaller n/m values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * and pick the better one if the error is equal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return rate * pdiv_best;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static long cdce925_clk_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) unsigned long l_parent_rate = *parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u16 divider = cdce925_calc_divider(rate, l_parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (l_parent_rate / divider != rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) l_parent_rate = cdce925_clk_best_parent_rate(hw, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) divider = cdce925_calc_divider(rate, l_parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) *parent_rate = l_parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (divider)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return (long)(l_parent_rate / divider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static int cdce925_clk_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct clk_cdce925_output *data = to_clk_cdce925_output(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) data->pdiv = cdce925_calc_divider(rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static const struct clk_ops cdce925_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .prepare = cdce925_clk_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .unprepare = cdce925_clk_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .recalc_rate = cdce925_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .round_rate = cdce925_clk_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .set_rate = cdce925_clk_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static u16 cdce925_y1_calc_divider(unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) unsigned long divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (!rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (rate >= parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) divider = DIV_ROUND_CLOSEST(parent_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (divider > 0x3FF) /* Y1 has 10-bit divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) divider = 0x3FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return (u16)divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static long cdce925_clk_y1_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) unsigned long l_parent_rate = *parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u16 divider = cdce925_y1_calc_divider(rate, l_parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (divider)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return (long)(l_parent_rate / divider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static int cdce925_clk_y1_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct clk_cdce925_output *data = to_clk_cdce925_output(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) data->pdiv = cdce925_y1_calc_divider(rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static const struct clk_ops cdce925_clk_y1_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .prepare = cdce925_clk_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .unprepare = cdce925_clk_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .recalc_rate = cdce925_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .round_rate = cdce925_clk_y1_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .set_rate = cdce925_clk_y1_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define CDCE925_I2C_COMMAND_BLOCK_TRANSFER 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define CDCE925_I2C_COMMAND_BYTE_TRANSFER 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static int cdce925_regmap_i2c_write(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) void *context, const void *data, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct device *dev = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct i2c_client *i2c = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u8 reg_data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (count != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /* First byte is command code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) reg_data[0] = CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)data)[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) reg_data[1] = ((u8 *)data)[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) dev_dbg(&i2c->dev, "%s(%zu) %#x %#x\n", __func__, count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) reg_data[0], reg_data[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ret = i2c_master_send(i2c, reg_data, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (likely(ret == count))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) else if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static int cdce925_regmap_i2c_read(void *context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) const void *reg, size_t reg_size, void *val, size_t val_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct device *dev = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct i2c_client *i2c = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct i2c_msg xfer[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) u8 reg_data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (reg_size != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) xfer[0].addr = i2c->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) xfer[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) xfer[0].buf = reg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (val_size == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) reg_data[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)reg)[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) xfer[0].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) reg_data[0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) CDCE925_I2C_COMMAND_BLOCK_TRANSFER | ((u8 *)reg)[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) reg_data[1] = val_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) xfer[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) xfer[1].addr = i2c->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) xfer[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) xfer[1].len = val_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) xfer[1].buf = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ret = i2c_transfer(i2c->adapter, xfer, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (likely(ret == 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) dev_dbg(&i2c->dev, "%s(%zu, %zu) %#x %#x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) reg_size, val_size, reg_data[0], *((u8 *)val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) } else if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static struct clk_hw *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) of_clk_cdce925_get(struct of_phandle_args *clkspec, void *_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) struct clk_cdce925_chip *data = _data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) unsigned int idx = clkspec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (idx >= ARRAY_SIZE(data->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) pr_err("%s: invalid index %u\n", __func__, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return &data->clk[idx].hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static void cdce925_regulator_disable(void *regulator)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) regulator_disable(regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static int cdce925_regulator_enable(struct device *dev, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct regulator *regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) regulator = devm_regulator_get(dev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (IS_ERR(regulator))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return PTR_ERR(regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) err = regulator_enable(regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) dev_err(dev, "Failed to enable %s: %d\n", name, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return devm_add_action_or_reset(dev, cdce925_regulator_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* The CDCE925 uses a funky way to read/write registers. Bulk mode is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * just weird, so just use the single byte mode exclusively. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static struct regmap_bus regmap_cdce925_bus = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .write = cdce925_regmap_i2c_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .read = cdce925_regmap_i2c_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static int cdce925_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct clk_cdce925_chip *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct device_node *node = client->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) const char *pll_clk_name[MAX_NUMBER_OF_PLLS] = {NULL,};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct device_node *np_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) char child_name[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct regmap_config config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .name = "configuration0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) dev_dbg(&client->dev, "%s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) err = cdce925_regulator_enable(&client->dev, "vdd");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) err = cdce925_regulator_enable(&client->dev, "vddout");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) data->i2c_client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) data->chip_info = &clk_cdce925_chip_info_tbl[id->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) config.max_register = CDCE925_OFFSET_PLL +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) data->chip_info->num_plls * 0x10 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) data->regmap = devm_regmap_init(&client->dev, ®map_cdce925_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) &client->dev, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (IS_ERR(data->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) dev_err(&client->dev, "failed to allocate register map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return PTR_ERR(data->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) i2c_set_clientdata(client, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) parent_name = of_clk_get_parent_name(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (!parent_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) dev_err(&client->dev, "missing parent clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) dev_dbg(&client->dev, "parent is: %s\n", parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (of_property_read_u32(node, "xtal-load-pf", &value) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) regmap_write(data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) CDCE925_REG_XCSEL, (value << 3) & 0xF8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* PWDN bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) regmap_update_bits(data->regmap, CDCE925_REG_GLOBAL1, BIT(4), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* Set input source for Y1 to be the XTAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) regmap_update_bits(data->regmap, 0x02, BIT(7), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) init.ops = &cdce925_pll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) /* Register PLL clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) for (i = 0; i < data->chip_info->num_plls; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) pll_clk_name[i] = kasprintf(GFP_KERNEL, "%pOFn.pll%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) client->dev.of_node, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) init.name = pll_clk_name[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) data->pll[i].chip = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) data->pll[i].hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) data->pll[i].index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) err = devm_clk_hw_register(&client->dev, &data->pll[i].hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) dev_err(&client->dev, "Failed register PLL %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) sprintf(child_name, "PLL%d", i+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) np_output = of_get_child_by_name(node, child_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (!np_output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (!of_property_read_u32(np_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) "clock-frequency", &value)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) err = clk_set_rate(data->pll[i].hw.clk, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) "unable to set PLL frequency %ud\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (!of_property_read_u32(np_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) "spread-spectrum", &value)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) u8 flag = of_property_read_bool(np_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) "spread-spectrum-center") ? 0x80 : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) regmap_update_bits(data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) 0x16 + (i*CDCE925_OFFSET_PLL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) 0x80, flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) regmap_update_bits(data->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) 0x12 + (i*CDCE925_OFFSET_PLL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) 0x07, value & 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) of_node_put(np_output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* Register output clock Y1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) init.ops = &cdce925_clk_y1_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) init.parent_names = &parent_name; /* Mux Y1 to input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) init.name = kasprintf(GFP_KERNEL, "%pOFn.Y1", client->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) data->clk[0].chip = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) data->clk[0].hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) data->clk[0].index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) data->clk[0].pdiv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) err = devm_clk_hw_register(&client->dev, &data->clk[0].hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) kfree(init.name); /* clock framework made a copy of the name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) dev_err(&client->dev, "clock registration Y1 failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /* Register output clocks Y2 .. Y5*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) init.ops = &cdce925_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) init.flags = CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) for (i = 1; i < data->chip_info->num_outputs; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) init.name = kasprintf(GFP_KERNEL, "%pOFn.Y%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) client->dev.of_node, i+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) data->clk[i].chip = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) data->clk[i].hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) data->clk[i].index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) data->clk[i].pdiv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) switch (i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* Mux Y2/3 to PLL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) init.parent_names = &pll_clk_name[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* Mux Y4/5 to PLL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) init.parent_names = &pll_clk_name[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* Mux Y6/7 to PLL3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) init.parent_names = &pll_clk_name[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) case 7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /* Mux Y8/9 to PLL4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) init.parent_names = &pll_clk_name[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) err = devm_clk_hw_register(&client->dev, &data->clk[i].hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) kfree(init.name); /* clock framework made a copy of the name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) dev_err(&client->dev, "clock registration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /* Register the output clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) err = of_clk_add_hw_provider(client->dev.of_node, of_clk_cdce925_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) dev_err(&client->dev, "unable to add OF clock provider\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) for (i = 0; i < data->chip_info->num_plls; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* clock framework made a copy of the name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) kfree(pll_clk_name[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static const struct i2c_device_id cdce925_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) { "cdce913", CDCE913 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) { "cdce925", CDCE925 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) { "cdce937", CDCE937 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) { "cdce949", CDCE949 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) MODULE_DEVICE_TABLE(i2c, cdce925_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static const struct of_device_id clk_cdce925_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) { .compatible = "ti,cdce913" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) { .compatible = "ti,cdce925" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) { .compatible = "ti,cdce937" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) { .compatible = "ti,cdce949" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) MODULE_DEVICE_TABLE(of, clk_cdce925_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static struct i2c_driver cdce925_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .name = "cdce925",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .of_match_table = of_match_ptr(clk_cdce925_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .probe = cdce925_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .id_table = cdce925_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) module_i2c_driver(cdce925_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) MODULE_DESCRIPTION("TI CDCE913/925/937/949 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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