^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Bitmain BM1880 SoC clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2019 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/clock/bm1880-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define BM1880_CLK_MPLL_CTL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define BM1880_CLK_SPLL_CTL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define BM1880_CLK_FPLL_CTL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define BM1880_CLK_DDRPLL_CTL 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define BM1880_CLK_ENABLE0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define BM1880_CLK_ENABLE1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define BM1880_CLK_SELECT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BM1880_CLK_DIV0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BM1880_CLK_DIV1 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BM1880_CLK_DIV2 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BM1880_CLK_DIV3 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BM1880_CLK_DIV4 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BM1880_CLK_DIV5 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BM1880_CLK_DIV6 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define BM1880_CLK_DIV7 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BM1880_CLK_DIV8 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BM1880_CLK_DIV9 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BM1880_CLK_DIV10 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BM1880_CLK_DIV11 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BM1880_CLK_DIV12 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BM1880_CLK_DIV13 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BM1880_CLK_DIV14 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define BM1880_CLK_DIV15 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BM1880_CLK_DIV16 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BM1880_CLK_DIV17 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BM1880_CLK_DIV18 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BM1880_CLK_DIV19 0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BM1880_CLK_DIV20 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define BM1880_CLK_DIV21 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define BM1880_CLK_DIV22 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define BM1880_CLK_DIV23 0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define BM1880_CLK_DIV24 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define BM1880_CLK_DIV25 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define BM1880_CLK_DIV26 0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define BM1880_CLK_DIV27 0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define BM1880_CLK_DIV28 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define to_bm1880_pll_clk(_hw) container_of(_hw, struct bm1880_pll_hw_clock, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define to_bm1880_div_clk(_hw) container_of(_hw, struct bm1880_div_hw_clock, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static DEFINE_SPINLOCK(bm1880_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct bm1880_clock_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) void __iomem *pll_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) void __iomem *sys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct clk_hw_onecell_data hw_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct bm1880_gate_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) const char *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 gate_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) s8 gate_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct bm1880_mux_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) const char * const *parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) s8 num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) s8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct bm1880_div_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u8 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 initval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) const struct clk_div_table *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct bm1880_div_hw_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct bm1880_div_clock div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct bm1880_composite_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) const char *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) const char * const *parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned int num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 gate_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 mux_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 div_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) s8 gate_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) s8 mux_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) s8 div_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) s8 div_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) s16 div_initval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) const struct clk_div_table *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct bm1880_pll_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct bm1880_pll_hw_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct bm1880_pll_clock pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const struct clk_ops bm1880_pll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static const struct clk_ops bm1880_clk_div_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define GATE_DIV(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) _div_shift, _div_width, _div_initval, _table, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) _flags) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .parent = _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .gate_reg = _gate_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .gate_shift = _gate_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .div_reg = _div_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .div_shift = _div_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .div_width = _div_width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .div_initval = _div_initval, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .table = _table, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .mux_shift = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .flags = _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define GATE_MUX(_id, _name, _parents, _gate_reg, _gate_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) _mux_reg, _mux_shift, _flags) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .parents = _parents, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .num_parents = ARRAY_SIZE(_parents), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .gate_reg = _gate_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .gate_shift = _gate_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .div_shift = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .mux_reg = _mux_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .mux_shift = _mux_shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .flags = _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CLK_PLL(_id, _name, _parent, _reg, _flags) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .pll.id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .pll.name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .pll.reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) &bm1880_pll_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) _flags), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CLK_DIV(_id, _name, _parent, _reg, _shift, _width, _initval, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) _table, _flags) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .div.id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .div.name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .div.reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .div.shift = _shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .div.width = _width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .div.initval = _initval, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .div.table = _table, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .hw.init = CLK_HW_INIT_HW(_name, _parent, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) &bm1880_clk_div_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) _flags), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static struct clk_parent_data bm1880_pll_parent[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { .fw_name = "osc", .name = "osc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * All PLL clocks are marked as CRITICAL, hence they are very crucial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * for the functioning of the SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static struct bm1880_pll_hw_clock bm1880_pll_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) CLK_PLL(BM1880_CLK_MPLL, "clk_mpll", bm1880_pll_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) BM1880_CLK_MPLL_CTL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) CLK_PLL(BM1880_CLK_SPLL, "clk_spll", bm1880_pll_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) BM1880_CLK_SPLL_CTL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) CLK_PLL(BM1880_CLK_FPLL, "clk_fpll", bm1880_pll_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) BM1880_CLK_FPLL_CTL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) CLK_PLL(BM1880_CLK_DDRPLL, "clk_ddrpll", bm1880_pll_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) BM1880_CLK_DDRPLL_CTL, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * Clocks marked as CRITICAL are needed for the proper functioning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * of the SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const struct bm1880_gate_clock bm1880_gate_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { BM1880_CLK_AHB_ROM, "clk_ahb_rom", "clk_mux_axi6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) BM1880_CLK_ENABLE0, 2, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { BM1880_CLK_AXI_SRAM, "clk_axi_sram", "clk_axi1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) BM1880_CLK_ENABLE0, 3, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * Since this clock is sourcing the DDR memory, let's mark it as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * critical to avoid gating.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { BM1880_CLK_DDR_AXI, "clk_ddr_axi", "clk_mux_axi6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) BM1880_CLK_ENABLE0, 4, CLK_IS_CRITICAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { BM1880_CLK_APB_EFUSE, "clk_apb_efuse", "clk_mux_axi6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) BM1880_CLK_ENABLE0, 6, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { BM1880_CLK_AXI5_EMMC, "clk_axi5_emmc", "clk_axi5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) BM1880_CLK_ENABLE0, 7, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { BM1880_CLK_AXI5_SD, "clk_axi5_sd", "clk_axi5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) BM1880_CLK_ENABLE0, 10, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { BM1880_CLK_AXI4_ETH0, "clk_axi4_eth0", "clk_axi4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) BM1880_CLK_ENABLE0, 14, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { BM1880_CLK_AXI4_ETH1, "clk_axi4_eth1", "clk_axi4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) BM1880_CLK_ENABLE0, 16, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { BM1880_CLK_AXI1_GDMA, "clk_axi1_gdma", "clk_axi1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) BM1880_CLK_ENABLE0, 17, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Don't gate GPIO clocks as it is not owned by the GPIO driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { BM1880_CLK_APB_GPIO, "clk_apb_gpio", "clk_mux_axi6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) BM1880_CLK_ENABLE0, 18, CLK_IGNORE_UNUSED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { BM1880_CLK_APB_GPIO_INTR, "clk_apb_gpio_intr", "clk_mux_axi6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) BM1880_CLK_ENABLE0, 19, CLK_IGNORE_UNUSED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { BM1880_CLK_AXI1_MINER, "clk_axi1_miner", "clk_axi1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) BM1880_CLK_ENABLE0, 21, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { BM1880_CLK_AHB_SF, "clk_ahb_sf", "clk_mux_axi6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) BM1880_CLK_ENABLE0, 22, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * Not sure which module this clock is sourcing but gating this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * prevents the system from booting. So, let's mark it as critical.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { BM1880_CLK_SDMA_AXI, "clk_sdma_axi", "clk_axi5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) BM1880_CLK_ENABLE0, 23, CLK_IS_CRITICAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { BM1880_CLK_APB_I2C, "clk_apb_i2c", "clk_mux_axi6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) BM1880_CLK_ENABLE0, 25, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { BM1880_CLK_APB_WDT, "clk_apb_wdt", "clk_mux_axi6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) BM1880_CLK_ENABLE0, 26, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) { BM1880_CLK_APB_JPEG, "clk_apb_jpeg", "clk_axi6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) BM1880_CLK_ENABLE0, 27, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { BM1880_CLK_AXI5_NF, "clk_axi5_nf", "clk_axi5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) BM1880_CLK_ENABLE0, 29, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { BM1880_CLK_APB_NF, "clk_apb_nf", "clk_axi6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) BM1880_CLK_ENABLE0, 30, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) { BM1880_CLK_APB_PWM, "clk_apb_pwm", "clk_mux_axi6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) BM1880_CLK_ENABLE1, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { BM1880_CLK_RV, "clk_rv", "clk_mux_rv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) BM1880_CLK_ENABLE1, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { BM1880_CLK_APB_SPI, "clk_apb_spi", "clk_mux_axi6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) BM1880_CLK_ENABLE1, 2, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) { BM1880_CLK_UART_500M, "clk_uart_500m", "clk_div_uart_500m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) BM1880_CLK_ENABLE1, 4, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) { BM1880_CLK_APB_UART, "clk_apb_uart", "clk_axi6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) BM1880_CLK_ENABLE1, 5, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) { BM1880_CLK_APB_I2S, "clk_apb_i2s", "clk_axi6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) BM1880_CLK_ENABLE1, 6, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { BM1880_CLK_AXI4_USB, "clk_axi4_usb", "clk_axi4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) BM1880_CLK_ENABLE1, 7, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) { BM1880_CLK_APB_USB, "clk_apb_usb", "clk_axi6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) BM1880_CLK_ENABLE1, 8, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { BM1880_CLK_12M_USB, "clk_12m_usb", "clk_div_12m_usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) BM1880_CLK_ENABLE1, 11, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { BM1880_CLK_APB_VIDEO, "clk_apb_video", "clk_axi6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) BM1880_CLK_ENABLE1, 12, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) { BM1880_CLK_APB_VPP, "clk_apb_vpp", "clk_axi6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) BM1880_CLK_ENABLE1, 15, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) { BM1880_CLK_AXI6, "clk_axi6", "clk_mux_axi6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) BM1880_CLK_ENABLE1, 21, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static const char * const clk_a53_parents[] = { "clk_spll", "clk_mpll" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static const char * const clk_rv_parents[] = { "clk_div_1_rv", "clk_div_0_rv" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const char * const clk_axi1_parents[] = { "clk_div_1_axi1", "clk_div_0_axi1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const char * const clk_axi6_parents[] = { "clk_div_1_axi6", "clk_div_0_axi6" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const struct bm1880_mux_clock bm1880_mux_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { BM1880_CLK_MUX_RV, "clk_mux_rv", clk_rv_parents, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) BM1880_CLK_SELECT, 1, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { BM1880_CLK_MUX_AXI6, "clk_mux_axi6", clk_axi6_parents, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) BM1880_CLK_SELECT, 3, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const struct clk_div_table bm1880_div_table_0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) { 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) { 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) { 12, 13 }, { 13, 14 }, { 14, 15 }, { 15, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { 16, 17 }, { 17, 18 }, { 18, 19 }, { 19, 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { 20, 21 }, { 21, 22 }, { 22, 23 }, { 23, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) { 24, 25 }, { 25, 26 }, { 26, 27 }, { 27, 28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { 28, 29 }, { 29, 30 }, { 30, 31 }, { 31, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const struct clk_div_table bm1880_div_table_1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) { 12, 13 }, { 13, 14 }, { 14, 15 }, { 15, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { 16, 17 }, { 17, 18 }, { 18, 19 }, { 19, 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { 20, 21 }, { 21, 22 }, { 22, 23 }, { 23, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { 24, 25 }, { 25, 26 }, { 26, 27 }, { 27, 28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { 28, 29 }, { 29, 30 }, { 30, 31 }, { 31, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { 127, 128 }, { 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static const struct clk_div_table bm1880_div_table_2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) { 12, 13 }, { 13, 14 }, { 14, 15 }, { 15, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { 16, 17 }, { 17, 18 }, { 18, 19 }, { 19, 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { 20, 21 }, { 21, 22 }, { 22, 23 }, { 23, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { 24, 25 }, { 25, 26 }, { 26, 27 }, { 27, 28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { 28, 29 }, { 29, 30 }, { 30, 31 }, { 31, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { 127, 128 }, { 255, 256 }, { 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static const struct clk_div_table bm1880_div_table_3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) { 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) { 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) { 12, 13 }, { 13, 14 }, { 14, 15 }, { 15, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { 16, 17 }, { 17, 18 }, { 18, 19 }, { 19, 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) { 20, 21 }, { 21, 22 }, { 22, 23 }, { 23, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) { 24, 25 }, { 25, 26 }, { 26, 27 }, { 27, 28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) { 28, 29 }, { 29, 30 }, { 30, 31 }, { 31, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) { 127, 128 }, { 255, 256 }, { 511, 512 }, { 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const struct clk_div_table bm1880_div_table_4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) { 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) { 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) { 12, 13 }, { 13, 14 }, { 14, 15 }, { 15, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { 16, 17 }, { 17, 18 }, { 18, 19 }, { 19, 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) { 20, 21 }, { 21, 22 }, { 22, 23 }, { 23, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { 24, 25 }, { 25, 26 }, { 26, 27 }, { 27, 28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) { 28, 29 }, { 29, 30 }, { 30, 31 }, { 31, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) { 127, 128 }, { 255, 256 }, { 511, 512 }, { 65535, 65536 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) { 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * Clocks marked as CRITICAL are needed for the proper functioning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * of the SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static struct bm1880_div_hw_clock bm1880_div_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) CLK_DIV(BM1880_CLK_DIV_0_RV, "clk_div_0_rv", &bm1880_pll_clks[1].hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) BM1880_CLK_DIV12, 16, 5, 1, bm1880_div_table_0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) CLK_DIV(BM1880_CLK_DIV_1_RV, "clk_div_1_rv", &bm1880_pll_clks[2].hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) BM1880_CLK_DIV13, 16, 5, 1, bm1880_div_table_0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) CLK_DIV(BM1880_CLK_DIV_UART_500M, "clk_div_uart_500m", &bm1880_pll_clks[2].hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) BM1880_CLK_DIV15, 16, 7, 3, bm1880_div_table_1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) CLK_DIV(BM1880_CLK_DIV_0_AXI1, "clk_div_0_axi1", &bm1880_pll_clks[0].hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) BM1880_CLK_DIV21, 16, 5, 2, bm1880_div_table_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) CLK_DIV(BM1880_CLK_DIV_1_AXI1, "clk_div_1_axi1", &bm1880_pll_clks[2].hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) BM1880_CLK_DIV22, 16, 5, 3, bm1880_div_table_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) CLK_DIV(BM1880_CLK_DIV_0_AXI6, "clk_div_0_axi6", &bm1880_pll_clks[2].hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) BM1880_CLK_DIV27, 16, 5, 15, bm1880_div_table_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) CLK_DIV(BM1880_CLK_DIV_1_AXI6, "clk_div_1_axi6", &bm1880_pll_clks[0].hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) BM1880_CLK_DIV28, 16, 5, 11, bm1880_div_table_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) CLK_DIV(BM1880_CLK_DIV_12M_USB, "clk_div_12m_usb", &bm1880_pll_clks[2].hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) BM1880_CLK_DIV18, 16, 7, 125, bm1880_div_table_1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * Clocks marked as CRITICAL are all needed for the proper functioning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * of the SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static struct bm1880_composite_clock bm1880_composite_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * Since clk_a53 and clk_50m_a53 clocks are sourcing the CPU core,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * let's mark them as critical to avoid gating.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) GATE_MUX(BM1880_CLK_A53, "clk_a53", clk_a53_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) BM1880_CLK_ENABLE0, 0, BM1880_CLK_SELECT, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) CLK_IS_CRITICAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) GATE_DIV(BM1880_CLK_50M_A53, "clk_50m_a53", "clk_fpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) BM1880_CLK_ENABLE0, 1, BM1880_CLK_DIV0, 16, 5, 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) bm1880_div_table_0, CLK_IS_CRITICAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) GATE_DIV(BM1880_CLK_EFUSE, "clk_efuse", "clk_fpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) BM1880_CLK_ENABLE0, 5, BM1880_CLK_DIV1, 16, 7, 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) bm1880_div_table_1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) GATE_DIV(BM1880_CLK_EMMC, "clk_emmc", "clk_fpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) BM1880_CLK_ENABLE0, 8, BM1880_CLK_DIV2, 16, 5, 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) bm1880_div_table_0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) GATE_DIV(BM1880_CLK_100K_EMMC, "clk_100k_emmc", "clk_div_12m_usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) BM1880_CLK_ENABLE0, 9, BM1880_CLK_DIV3, 16, 8, 120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) bm1880_div_table_2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) GATE_DIV(BM1880_CLK_SD, "clk_sd", "clk_fpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) BM1880_CLK_ENABLE0, 11, BM1880_CLK_DIV4, 16, 5, 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) bm1880_div_table_0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) GATE_DIV(BM1880_CLK_100K_SD, "clk_100k_sd", "clk_div_12m_usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) BM1880_CLK_ENABLE0, 12, BM1880_CLK_DIV5, 16, 8, 120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) bm1880_div_table_2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) GATE_DIV(BM1880_CLK_500M_ETH0, "clk_500m_eth0", "clk_fpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) BM1880_CLK_ENABLE0, 13, BM1880_CLK_DIV6, 16, 5, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) bm1880_div_table_0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) GATE_DIV(BM1880_CLK_500M_ETH1, "clk_500m_eth1", "clk_fpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) BM1880_CLK_ENABLE0, 15, BM1880_CLK_DIV7, 16, 5, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) bm1880_div_table_0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* Don't gate GPIO clocks as it is not owned by the GPIO driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) GATE_DIV(BM1880_CLK_GPIO_DB, "clk_gpio_db", "clk_div_12m_usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) BM1880_CLK_ENABLE0, 20, BM1880_CLK_DIV8, 16, 16, 120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) bm1880_div_table_4, CLK_IGNORE_UNUSED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) GATE_DIV(BM1880_CLK_SDMA_AUD, "clk_sdma_aud", "clk_fpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) BM1880_CLK_ENABLE0, 24, BM1880_CLK_DIV9, 16, 7, 61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) bm1880_div_table_1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) GATE_DIV(BM1880_CLK_JPEG_AXI, "clk_jpeg_axi", "clk_fpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) BM1880_CLK_ENABLE0, 28, BM1880_CLK_DIV10, 16, 5, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) bm1880_div_table_0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) GATE_DIV(BM1880_CLK_NF, "clk_nf", "clk_fpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) BM1880_CLK_ENABLE0, 31, BM1880_CLK_DIV11, 16, 5, 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) bm1880_div_table_0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) GATE_DIV(BM1880_CLK_TPU_AXI, "clk_tpu_axi", "clk_spll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) BM1880_CLK_ENABLE1, 3, BM1880_CLK_DIV14, 16, 5, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) bm1880_div_table_0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) GATE_DIV(BM1880_CLK_125M_USB, "clk_125m_usb", "clk_fpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) BM1880_CLK_ENABLE1, 9, BM1880_CLK_DIV16, 16, 5, 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) bm1880_div_table_0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) GATE_DIV(BM1880_CLK_33K_USB, "clk_33k_usb", "clk_div_12m_usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) BM1880_CLK_ENABLE1, 10, BM1880_CLK_DIV17, 16, 9, 363,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) bm1880_div_table_3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) GATE_DIV(BM1880_CLK_VIDEO_AXI, "clk_video_axi", "clk_fpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) BM1880_CLK_ENABLE1, 13, BM1880_CLK_DIV19, 16, 5, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) bm1880_div_table_0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) GATE_DIV(BM1880_CLK_VPP_AXI, "clk_vpp_axi", "clk_fpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) BM1880_CLK_ENABLE1, 14, BM1880_CLK_DIV20, 16, 5, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) bm1880_div_table_0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) GATE_MUX(BM1880_CLK_AXI1, "clk_axi1", clk_axi1_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) BM1880_CLK_ENABLE1, 15, BM1880_CLK_SELECT, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) GATE_DIV(BM1880_CLK_AXI2, "clk_axi2", "clk_fpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) BM1880_CLK_ENABLE1, 17, BM1880_CLK_DIV23, 16, 5, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) bm1880_div_table_0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) GATE_DIV(BM1880_CLK_AXI3, "clk_axi3", "clk_mux_rv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) BM1880_CLK_ENABLE1, 18, BM1880_CLK_DIV24, 16, 5, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) bm1880_div_table_0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) GATE_DIV(BM1880_CLK_AXI4, "clk_axi4", "clk_fpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) BM1880_CLK_ENABLE1, 19, BM1880_CLK_DIV25, 16, 5, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) bm1880_div_table_0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) GATE_DIV(BM1880_CLK_AXI5, "clk_axi5", "clk_fpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) BM1880_CLK_ENABLE1, 20, BM1880_CLK_DIV26, 16, 5, 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) bm1880_div_table_0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static unsigned long bm1880_pll_rate_calc(u32 regval, unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) u64 numerator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u32 fbdiv, refdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u32 postdiv1, postdiv2, denominator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) fbdiv = (regval >> 16) & 0xfff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) refdiv = regval & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) postdiv1 = (regval >> 8) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) postdiv2 = (regval >> 12) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) numerator = parent_rate * fbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) denominator = refdiv * postdiv1 * postdiv2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) do_div(numerator, denominator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return (unsigned long)numerator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static unsigned long bm1880_pll_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct bm1880_pll_hw_clock *pll_hw = to_bm1880_pll_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) regval = readl(pll_hw->base + pll_hw->pll.reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) rate = bm1880_pll_rate_calc(regval, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static const struct clk_ops bm1880_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .recalc_rate = bm1880_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static struct clk_hw *bm1880_clk_register_pll(struct bm1880_pll_hw_clock *pll_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) void __iomem *sys_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) pll_clk->base = sys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) hw = &pll_clk->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) err = clk_hw_register(NULL, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static int bm1880_clk_register_plls(struct bm1880_pll_hw_clock *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) int num_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct bm1880_clock_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) void __iomem *pll_base = data->pll_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) for (i = 0; i < num_clks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct bm1880_pll_hw_clock *bm1880_clk = &clks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) hw = bm1880_clk_register_pll(bm1880_clk, pll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (IS_ERR(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) pr_err("%s: failed to register clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) __func__, bm1880_clk->pll.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) data->hw_data.hws[clks[i].pll.id] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) while (i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) clk_hw_unregister(data->hw_data.hws[clks[i].pll.id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static int bm1880_clk_register_mux(const struct bm1880_mux_clock *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) int num_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct bm1880_clock_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) void __iomem *sys_base = data->sys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) for (i = 0; i < num_clks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) hw = clk_hw_register_mux(NULL, clks[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) clks[i].parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) clks[i].num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) clks[i].flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) sys_base + clks[i].reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) clks[i].shift, 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) &bm1880_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (IS_ERR(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) pr_err("%s: failed to register clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) __func__, clks[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) data->hw_data.hws[clks[i].id] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) while (i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) clk_hw_unregister_mux(data->hw_data.hws[clks[i].id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static unsigned long bm1880_clk_div_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct bm1880_div_hw_clock *div_hw = to_bm1880_div_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct bm1880_div_clock *div = &div_hw->div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) void __iomem *reg_addr = div_hw->base + div->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (!(readl(reg_addr) & BIT(3))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) val = div->initval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) val = readl(reg_addr) >> div->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) val &= clk_div_mask(div->width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) rate = divider_recalc_rate(hw, parent_rate, val, div->table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) div->flags, div->width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static long bm1880_clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) unsigned long *prate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct bm1880_div_hw_clock *div_hw = to_bm1880_div_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct bm1880_div_clock *div = &div_hw->div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) void __iomem *reg_addr = div_hw->base + div->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (div->flags & CLK_DIVIDER_READ_ONLY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) val = readl(reg_addr) >> div->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) val &= clk_div_mask(div->width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return divider_ro_round_rate(hw, rate, prate, div->table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) div->width, div->flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return divider_round_rate(hw, rate, prate, div->table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) div->width, div->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static int bm1880_clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct bm1880_div_hw_clock *div_hw = to_bm1880_div_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct bm1880_div_clock *div = &div_hw->div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) void __iomem *reg_addr = div_hw->base + div->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) unsigned long flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) value = divider_get_val(rate, parent_rate, div->table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) div->width, div_hw->div.flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (value < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (div_hw->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) spin_lock_irqsave(div_hw->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) __acquire(div_hw->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) val = readl(reg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) val &= ~(clk_div_mask(div->width) << div_hw->div.shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) val |= (u32)value << div->shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) writel(val, reg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (div_hw->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) spin_unlock_irqrestore(div_hw->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) __release(div_hw->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static const struct clk_ops bm1880_clk_div_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .recalc_rate = bm1880_clk_div_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .round_rate = bm1880_clk_div_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .set_rate = bm1880_clk_div_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static struct clk_hw *bm1880_clk_register_div(struct bm1880_div_hw_clock *div_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) void __iomem *sys_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) div_clk->div.flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) div_clk->base = sys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) div_clk->lock = &bm1880_clk_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) hw = &div_clk->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) err = clk_hw_register(NULL, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static int bm1880_clk_register_divs(struct bm1880_div_hw_clock *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) int num_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct bm1880_clock_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) void __iomem *sys_base = data->sys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) unsigned int i, id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) for (i = 0; i < num_clks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) struct bm1880_div_hw_clock *bm1880_clk = &clks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) hw = bm1880_clk_register_div(bm1880_clk, sys_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (IS_ERR(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) pr_err("%s: failed to register clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) __func__, bm1880_clk->div.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) id = clks[i].div.id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) data->hw_data.hws[id] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) while (i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) clk_hw_unregister(data->hw_data.hws[clks[i].div.id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static int bm1880_clk_register_gate(const struct bm1880_gate_clock *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) int num_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct bm1880_clock_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) void __iomem *sys_base = data->sys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) for (i = 0; i < num_clks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) hw = clk_hw_register_gate(NULL, clks[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) clks[i].parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) clks[i].flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) sys_base + clks[i].gate_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) clks[i].gate_shift, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) &bm1880_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (IS_ERR(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) pr_err("%s: failed to register clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) __func__, clks[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) data->hw_data.hws[clks[i].id] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) while (i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) clk_hw_unregister_gate(data->hw_data.hws[clks[i].id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static struct clk_hw *bm1880_clk_register_composite(struct bm1880_composite_clock *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) void __iomem *sys_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct clk_mux *mux = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct clk_gate *gate = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) struct bm1880_div_hw_clock *div_hws = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) struct clk_hw *mux_hw = NULL, *gate_hw = NULL, *div_hw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) const struct clk_ops *mux_ops = NULL, *gate_ops = NULL, *div_ops = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) const char * const *parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) const char *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) int num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (clks->mux_shift >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) mux = kzalloc(sizeof(*mux), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (!mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) mux->reg = sys_base + clks->mux_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) mux->mask = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) mux->shift = clks->mux_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) mux_hw = &mux->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) mux_ops = &clk_mux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) mux->lock = &bm1880_clk_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) parent_names = clks->parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) num_parents = clks->num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) parent = clks->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) parent_names = &parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (clks->gate_shift >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) gate = kzalloc(sizeof(*gate), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (!gate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) gate->reg = sys_base + clks->gate_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) gate->bit_idx = clks->gate_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) gate->lock = &bm1880_clk_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) gate_hw = &gate->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) gate_ops = &clk_gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (clks->div_shift >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) div_hws = kzalloc(sizeof(*div_hws), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (!div_hws) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) div_hws->base = sys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) div_hws->div.reg = clks->div_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) div_hws->div.shift = clks->div_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) div_hws->div.width = clks->div_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) div_hws->div.table = clks->table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) div_hws->div.initval = clks->div_initval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) div_hws->lock = &bm1880_clk_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) div_hws->div.flags = CLK_DIVIDER_ONE_BASED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) CLK_DIVIDER_ALLOW_ZERO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) div_hw = &div_hws->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) div_ops = &bm1880_clk_div_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) hw = clk_hw_register_composite(NULL, clks->name, parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) num_parents, mux_hw, mux_ops, div_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) div_ops, gate_hw, gate_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) clks->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (IS_ERR(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ret = PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) kfree(div_hws);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) kfree(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) kfree(mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static int bm1880_clk_register_composites(struct bm1880_composite_clock *clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) int num_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) struct bm1880_clock_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) void __iomem *sys_base = data->sys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) for (i = 0; i < num_clks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct bm1880_composite_clock *bm1880_clk = &clks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) hw = bm1880_clk_register_composite(bm1880_clk, sys_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (IS_ERR(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) pr_err("%s: failed to register clock %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) __func__, bm1880_clk->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) data->hw_data.hws[clks[i].id] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) while (i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) clk_hw_unregister_composite(data->hw_data.hws[clks[i].id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) return PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static int bm1880_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct bm1880_clock_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) void __iomem *pll_base, *sys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) int num_clks, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) pll_base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (IS_ERR(pll_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return PTR_ERR(pll_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) sys_base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (IS_ERR(sys_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return PTR_ERR(sys_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) num_clks = ARRAY_SIZE(bm1880_pll_clks) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) ARRAY_SIZE(bm1880_div_clks) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) ARRAY_SIZE(bm1880_mux_clks) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) ARRAY_SIZE(bm1880_composite_clks) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) ARRAY_SIZE(bm1880_gate_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) num_clks), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) clk_data->pll_base = pll_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) clk_data->sys_base = sys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) for (i = 0; i < num_clks; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) clk_data->hw_data.hws[i] = ERR_PTR(-ENOENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) clk_data->hw_data.num = num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) bm1880_clk_register_plls(bm1880_pll_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) ARRAY_SIZE(bm1880_pll_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) bm1880_clk_register_divs(bm1880_div_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) ARRAY_SIZE(bm1880_div_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) bm1880_clk_register_mux(bm1880_mux_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) ARRAY_SIZE(bm1880_mux_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) bm1880_clk_register_composites(bm1880_composite_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) ARRAY_SIZE(bm1880_composite_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) bm1880_clk_register_gate(bm1880_gate_clks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) ARRAY_SIZE(bm1880_gate_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) &clk_data->hw_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static const struct of_device_id bm1880_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) { .compatible = "bitmain,bm1880-clk", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) MODULE_DEVICE_TABLE(of, bm1880_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static struct platform_driver bm1880_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .name = "bm1880-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .of_match_table = bm1880_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .probe = bm1880_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) module_platform_driver(bm1880_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) MODULE_DESCRIPTION("Clock driver for Bitmain BM1880 SoC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags