^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/clk/clk-axm5516.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Provides clock implementations for three different types of clock devices on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * the Axxia device: PLL clock, a clock divider and a clock mux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2014 LSI Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <dt-bindings/clock/lsi,axm5516-clks.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * struct axxia_clk - Common struct to all Axxia clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * @hw: clk_hw for the common clk framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * @regmap: Regmap for the clock control registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct axxia_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define to_axxia_clk(_hw) container_of(_hw, struct axxia_clk, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * struct axxia_pllclk - Axxia PLL generated clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * @aclk: Common struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * @reg: Offset into regmap for PLL control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct axxia_pllclk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct axxia_clk aclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define to_axxia_pllclk(_aclk) container_of(_aclk, struct axxia_pllclk, aclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * axxia_pllclk_recalc - Calculate the PLL generated clock rate given the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * parent clock rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) axxia_pllclk_recalc(struct clk_hw *hw, unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct axxia_clk *aclk = to_axxia_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct axxia_pllclk *pll = to_axxia_pllclk(aclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned long rate, fbdiv, refdiv, postdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) regmap_read(aclk->regmap, pll->reg, &control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) postdiv = ((control >> 0) & 0xf) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) fbdiv = ((control >> 4) & 0xfff) + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) refdiv = ((control >> 16) & 0x1f) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) rate = (parent_rate / (refdiv * postdiv)) * fbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static const struct clk_ops axxia_pllclk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .recalc_rate = axxia_pllclk_recalc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * struct axxia_divclk - Axxia clock divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @aclk: Common struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @reg: Offset into regmap for PLL control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @shift: Bit position for divider value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * @width: Number of bits in divider value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct axxia_divclk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct axxia_clk aclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define to_axxia_divclk(_aclk) container_of(_aclk, struct axxia_divclk, aclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * axxia_divclk_recalc_rate - Calculate clock divider output rage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) axxia_divclk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct axxia_clk *aclk = to_axxia_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct axxia_divclk *divclk = to_axxia_divclk(aclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 ctrl, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) regmap_read(aclk->regmap, divclk->reg, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) div = 1 + ((ctrl >> divclk->shift) & ((1 << divclk->width)-1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return parent_rate / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static const struct clk_ops axxia_divclk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .recalc_rate = axxia_divclk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * struct axxia_clkmux - Axxia clock mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @aclk: Common struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @reg: Offset into regmap for PLL control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @shift: Bit position for selection value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * @width: Number of bits in selection value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct axxia_clkmux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct axxia_clk aclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define to_axxia_clkmux(_aclk) container_of(_aclk, struct axxia_clkmux, aclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * axxia_clkmux_get_parent - Return the index of selected parent clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static u8 axxia_clkmux_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct axxia_clk *aclk = to_axxia_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct axxia_clkmux *mux = to_axxia_clkmux(aclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 ctrl, parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) regmap_read(aclk->regmap, mux->reg, &ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) parent = (ctrl >> mux->shift) & ((1 << mux->width) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return (u8) parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static const struct clk_ops axxia_clkmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .get_parent = axxia_clkmux_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * PLLs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static struct axxia_pllclk clk_fab_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .aclk.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .name = "clk_fab_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) "clk_ref0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .ops = &axxia_pllclk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .reg = 0x01800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static struct axxia_pllclk clk_cpu_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .aclk.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .name = "clk_cpu_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) "clk_ref0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .ops = &axxia_pllclk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .reg = 0x02000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static struct axxia_pllclk clk_sys_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .aclk.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .name = "clk_sys_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) "clk_ref0"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .ops = &axxia_pllclk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .reg = 0x02800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static struct axxia_pllclk clk_sm0_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .aclk.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .name = "clk_sm0_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) "clk_ref2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .ops = &axxia_pllclk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .reg = 0x03000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static struct axxia_pllclk clk_sm1_pll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .aclk.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .name = "clk_sm1_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) "clk_ref1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .ops = &axxia_pllclk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .reg = 0x03800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * Clock dividers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static struct axxia_divclk clk_cpu0_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .aclk.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .name = "clk_cpu0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) "clk_cpu_pll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .ops = &axxia_divclk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .reg = 0x10008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static struct axxia_divclk clk_cpu1_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .aclk.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .name = "clk_cpu1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) "clk_cpu_pll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .ops = &axxia_divclk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .reg = 0x10008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static struct axxia_divclk clk_cpu2_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .aclk.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .name = "clk_cpu2_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) "clk_cpu_pll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .ops = &axxia_divclk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .reg = 0x10008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static struct axxia_divclk clk_cpu3_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .aclk.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .name = "clk_cpu3_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) "clk_cpu_pll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .ops = &axxia_divclk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .reg = 0x10008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static struct axxia_divclk clk_nrcp_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .aclk.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .name = "clk_nrcp_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) "clk_sys_pll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .ops = &axxia_divclk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .reg = 0x1000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static struct axxia_divclk clk_sys_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .aclk.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .name = "clk_sys_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) "clk_sys_pll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .ops = &axxia_divclk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .reg = 0x1000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static struct axxia_divclk clk_fab_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .aclk.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .name = "clk_fab_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) "clk_fab_pll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .ops = &axxia_divclk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .reg = 0x1000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static struct axxia_divclk clk_per_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .aclk.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .name = "clk_per_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) "clk_sm1_pll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .ops = &axxia_divclk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .reg = 0x1000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static struct axxia_divclk clk_mmc_div = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .aclk.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .name = "clk_mmc_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) "clk_sm1_pll"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .ops = &axxia_divclk_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .reg = 0x1000c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * Clock MUXes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static struct axxia_clkmux clk_cpu0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .aclk.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .name = "clk_cpu0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) "clk_ref0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) "clk_cpu_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) "clk_cpu0_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) "clk_cpu0_div"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .ops = &axxia_clkmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .reg = 0x10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static struct axxia_clkmux clk_cpu1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .aclk.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .name = "clk_cpu1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) "clk_ref0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) "clk_cpu_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) "clk_cpu1_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) "clk_cpu1_div"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .ops = &axxia_clkmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .reg = 0x10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .shift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static struct axxia_clkmux clk_cpu2_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .aclk.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .name = "clk_cpu2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) "clk_ref0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) "clk_cpu_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) "clk_cpu2_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) "clk_cpu2_div"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .ops = &axxia_clkmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .reg = 0x10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static struct axxia_clkmux clk_cpu3_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .aclk.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .name = "clk_cpu3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) "clk_ref0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) "clk_cpu_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) "clk_cpu3_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) "clk_cpu3_div"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .ops = &axxia_clkmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .reg = 0x10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static struct axxia_clkmux clk_nrcp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .aclk.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .name = "clk_nrcp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) "clk_ref0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) "clk_sys_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) "clk_nrcp_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) "clk_nrcp_div"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .ops = &axxia_clkmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .reg = 0x10004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static struct axxia_clkmux clk_sys_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .aclk.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .name = "clk_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) "clk_ref0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) "clk_sys_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) "clk_sys_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) "clk_sys_div"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .ops = &axxia_clkmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .reg = 0x10004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .shift = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static struct axxia_clkmux clk_fab_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .aclk.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .name = "clk_fab",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) "clk_ref0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) "clk_fab_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) "clk_fab_div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) "clk_fab_div"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .num_parents = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .ops = &axxia_clkmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .reg = 0x10004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .width = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static struct axxia_clkmux clk_per_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .aclk.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .name = "clk_per",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) "clk_ref1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) "clk_per_div"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .ops = &axxia_clkmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .reg = 0x10004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static struct axxia_clkmux clk_mmc_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .aclk.hw.init = &(struct clk_init_data){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .name = "clk_mmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .parent_names = (const char *[]){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) "clk_ref1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) "clk_mmc_div"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .num_parents = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .ops = &axxia_clkmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .reg = 0x10004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .shift = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .width = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* Table of all supported clocks indexed by the clock identifiers from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * device tree binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static struct axxia_clk *axmclk_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) [AXXIA_CLK_FAB_PLL] = &clk_fab_pll.aclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) [AXXIA_CLK_CPU_PLL] = &clk_cpu_pll.aclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) [AXXIA_CLK_SYS_PLL] = &clk_sys_pll.aclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) [AXXIA_CLK_SM0_PLL] = &clk_sm0_pll.aclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) [AXXIA_CLK_SM1_PLL] = &clk_sm1_pll.aclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) [AXXIA_CLK_FAB_DIV] = &clk_fab_div.aclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) [AXXIA_CLK_SYS_DIV] = &clk_sys_div.aclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) [AXXIA_CLK_NRCP_DIV] = &clk_nrcp_div.aclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) [AXXIA_CLK_CPU0_DIV] = &clk_cpu0_div.aclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) [AXXIA_CLK_CPU1_DIV] = &clk_cpu1_div.aclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) [AXXIA_CLK_CPU2_DIV] = &clk_cpu2_div.aclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) [AXXIA_CLK_CPU3_DIV] = &clk_cpu3_div.aclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) [AXXIA_CLK_PER_DIV] = &clk_per_div.aclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) [AXXIA_CLK_MMC_DIV] = &clk_mmc_div.aclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) [AXXIA_CLK_FAB] = &clk_fab_mux.aclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) [AXXIA_CLK_SYS] = &clk_sys_mux.aclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) [AXXIA_CLK_NRCP] = &clk_nrcp_mux.aclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) [AXXIA_CLK_CPU0] = &clk_cpu0_mux.aclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) [AXXIA_CLK_CPU1] = &clk_cpu1_mux.aclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) [AXXIA_CLK_CPU2] = &clk_cpu2_mux.aclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) [AXXIA_CLK_CPU3] = &clk_cpu3_mux.aclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) [AXXIA_CLK_PER] = &clk_per_mux.aclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) [AXXIA_CLK_MMC] = &clk_mmc_mux.aclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static struct clk_hw *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) of_clk_axmclk_get(struct of_phandle_args *clkspec, void *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) unsigned int idx = clkspec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (idx >= ARRAY_SIZE(axmclk_clocks)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) pr_err("%s: invalid index %u\n", __func__, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return &axmclk_clocks[idx]->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static const struct regmap_config axmclk_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .max_register = 0x1fffc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .fast_io = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static const struct of_device_id axmclk_match_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) { .compatible = "lsi,axm5516-clks" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) MODULE_DEVICE_TABLE(of, axmclk_match_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static int axmclk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) size_t num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) regmap = devm_regmap_init_mmio(dev, base, &axmclk_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) num_clks = ARRAY_SIZE(axmclk_clocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) pr_info("axmclk: supporting %zu clocks\n", num_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* Update each entry with the allocated regmap and register the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * with the common clock framework
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) for (i = 0; i < num_clks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) axmclk_clocks[i]->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ret = devm_clk_hw_register(dev, &axmclk_clocks[i]->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return of_clk_add_hw_provider(dev->of_node, of_clk_axmclk_get, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static int axmclk_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) of_clk_del_provider(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static struct platform_driver axmclk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .probe = axmclk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .remove = axmclk_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .name = "clk-axm5516",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .of_match_table = axmclk_match_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static int __init axmclk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return platform_driver_register(&axmclk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) core_initcall(axmclk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static void __exit axmclk_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) platform_driver_unregister(&axmclk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) module_exit(axmclk_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) MODULE_DESCRIPTION("AXM5516 clock driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) MODULE_ALIAS("platform:clk-axm5516");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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