Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * AXI clkgen driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2012-2013 Analog Devices Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Author: Lars-Peter Clausen <lars@metafoo.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define AXI_CLKGEN_V2_REG_RESET		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define AXI_CLKGEN_V2_REG_CLKSEL	0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define AXI_CLKGEN_V2_REG_DRP_CNTRL	0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define AXI_CLKGEN_V2_REG_DRP_STATUS	0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define AXI_CLKGEN_V2_RESET_MMCM_ENABLE	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define AXI_CLKGEN_V2_RESET_ENABLE	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define AXI_CLKGEN_V2_DRP_CNTRL_SEL	BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define AXI_CLKGEN_V2_DRP_CNTRL_READ	BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define AXI_CLKGEN_V2_DRP_STATUS_BUSY	BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MMCM_REG_CLKOUT5_2	0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define MMCM_REG_CLKOUT0_1	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define MMCM_REG_CLKOUT0_2	0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MMCM_REG_CLKOUT6_2	0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define MMCM_REG_CLK_FB1	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define MMCM_REG_CLK_FB2	0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MMCM_REG_CLK_DIV	0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MMCM_REG_LOCK1		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define MMCM_REG_LOCK2		0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MMCM_REG_LOCK3		0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define MMCM_REG_POWER		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define MMCM_REG_FILTER1	0x4e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define MMCM_REG_FILTER2	0x4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define MMCM_CLKOUT_NOCOUNT	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define MMCM_CLK_DIV_DIVIDE	BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define MMCM_CLK_DIV_NOCOUNT	BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) struct axi_clkgen {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct clk_hw clk_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static uint32_t axi_clkgen_lookup_filter(unsigned int m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	switch (m) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		return 0x01001990;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		return 0x01001190;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		return 0x01009890;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		return 0x01001890;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		return 0x01008890;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	case 5 ... 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		return 0x01009090;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	case 9 ... 11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		return 0x01000890;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	case 12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		return 0x08009090;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	case 13 ... 22:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		return 0x01001090;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	case 23 ... 36:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		return 0x01008090;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	case 37 ... 46:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		return 0x08001090;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		return 0x08008090;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) static const uint32_t axi_clkgen_lock_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	0x060603e8, 0x060603e8, 0x080803e8, 0x0b0b03e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	0x0e0e03e8, 0x111103e8, 0x131303e8, 0x161603e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	0x191903e8, 0x1c1c03e8, 0x1f1f0384, 0x1f1f0339,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	0x1f1f02ee, 0x1f1f02bc, 0x1f1f028a, 0x1f1f0271,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	0x1f1f023f, 0x1f1f0226, 0x1f1f020d, 0x1f1f01f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	0x1f1f01db, 0x1f1f01c2, 0x1f1f01a9, 0x1f1f0190,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	0x1f1f0190, 0x1f1f0177, 0x1f1f015e, 0x1f1f015e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	0x1f1f0145, 0x1f1f0145, 0x1f1f012c, 0x1f1f012c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	0x1f1f012c, 0x1f1f0113, 0x1f1f0113, 0x1f1f0113,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static uint32_t axi_clkgen_lookup_lock(unsigned int m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	if (m < ARRAY_SIZE(axi_clkgen_lock_table))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		return axi_clkgen_lock_table[m];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	return 0x1f1f00fa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const unsigned int fpfd_min = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const unsigned int fpfd_max = 300000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const unsigned int fvco_min = 600000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static const unsigned int fvco_max = 1200000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void axi_clkgen_calc_params(unsigned long fin, unsigned long fout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	unsigned int *best_d, unsigned int *best_m, unsigned int *best_dout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	unsigned long d, d_min, d_max, _d_min, _d_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	unsigned long m, m_min, m_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	unsigned long f, dout, best_f, fvco;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	unsigned long fract_shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	unsigned long fvco_min_fract, fvco_max_fract;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	fin /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	fout /= 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	best_f = ULONG_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	*best_d = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	*best_m = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	*best_dout = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	d_min = max_t(unsigned long, DIV_ROUND_UP(fin, fpfd_max), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	d_max = min_t(unsigned long, fin / fpfd_min, 80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) again:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	fvco_min_fract = fvco_min << fract_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	fvco_max_fract = fvco_max << fract_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	m_min = max_t(unsigned long, DIV_ROUND_UP(fvco_min_fract, fin) * d_min, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	m_max = min_t(unsigned long, fvco_max_fract * d_max / fin, 64 << fract_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	for (m = m_min; m <= m_max; m++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		_d_min = max(d_min, DIV_ROUND_UP(fin * m, fvco_max_fract));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		_d_max = min(d_max, fin * m / fvco_min_fract);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		for (d = _d_min; d <= _d_max; d++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			fvco = fin * m / d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			dout = DIV_ROUND_CLOSEST(fvco, fout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			dout = clamp_t(unsigned long, dout, 1, 128 << fract_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			f = fvco / dout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			if (abs(f - fout) < abs(best_f - fout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 				best_f = f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 				*best_d = d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 				*best_m = m << (3 - fract_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 				*best_dout = dout << (3 - fract_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 				if (best_f == fout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 					return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	/* Lets see if we find a better setting in fractional mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	if (fract_shift == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		fract_shift = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		goto again;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct axi_clkgen_div_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	unsigned int low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	unsigned int high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	unsigned int edge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	unsigned int nocount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	unsigned int frac_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	unsigned int frac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	unsigned int frac_wf_f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	unsigned int frac_wf_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	unsigned int frac_phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void axi_clkgen_calc_clk_params(unsigned int divider,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	unsigned int frac_divider, struct axi_clkgen_div_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	memset(params, 0x0, sizeof(*params));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	if (divider == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		params->nocount = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (frac_divider == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		params->high = divider / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		params->edge = divider % 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		params->low = divider - params->high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		params->frac_en = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		params->frac = frac_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		params->high = divider / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		params->edge = divider % 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		params->low = params->high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		if (params->edge == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			params->high--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			params->frac_wf_r = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		if (params->edge == 0 || frac_divider == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			params->low--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		if (((params->edge == 0) ^ (frac_divider == 1)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			(divider == 2 && frac_divider == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			params->frac_wf_f = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		params->frac_phase = params->edge * 4 + frac_divider / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static void axi_clkgen_write(struct axi_clkgen *axi_clkgen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	unsigned int reg, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	writel(val, axi_clkgen->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static void axi_clkgen_read(struct axi_clkgen *axi_clkgen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	unsigned int reg, unsigned int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	*val = readl(axi_clkgen->base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int axi_clkgen_wait_non_busy(struct axi_clkgen *axi_clkgen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	unsigned int timeout = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_STATUS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	} while ((val & AXI_CLKGEN_V2_DRP_STATUS_BUSY) && --timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (val & AXI_CLKGEN_V2_DRP_STATUS_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	return val & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	unsigned int reg, unsigned int *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	unsigned int reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	ret = axi_clkgen_wait_non_busy(axi_clkgen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	reg_val = AXI_CLKGEN_V2_DRP_CNTRL_SEL | AXI_CLKGEN_V2_DRP_CNTRL_READ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	reg_val |= (reg << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	ret = axi_clkgen_wait_non_busy(axi_clkgen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	*val = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	unsigned int reg, unsigned int val, unsigned int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	unsigned int reg_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	ret = axi_clkgen_wait_non_busy(axi_clkgen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	if (mask != 0xffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		axi_clkgen_mmcm_read(axi_clkgen, reg, &reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		reg_val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	reg_val |= AXI_CLKGEN_V2_DRP_CNTRL_SEL | (reg << 16) | (val & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	unsigned int val = AXI_CLKGEN_V2_RESET_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		val |= AXI_CLKGEN_V2_RESET_MMCM_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_RESET, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static struct axi_clkgen *clk_hw_to_axi_clkgen(struct clk_hw *clk_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	return container_of(clk_hw, struct axi_clkgen, clk_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static void axi_clkgen_set_div(struct axi_clkgen *axi_clkgen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	unsigned int reg1, unsigned int reg2, unsigned int reg3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	struct axi_clkgen_div_params *params)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	axi_clkgen_mmcm_write(axi_clkgen, reg1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		(params->high << 6) | params->low, 0xefff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	axi_clkgen_mmcm_write(axi_clkgen, reg2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		(params->frac << 12) | (params->frac_en << 11) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		(params->frac_wf_r << 10) | (params->edge << 7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		(params->nocount << 6), 0x7fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	if (reg3 != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		axi_clkgen_mmcm_write(axi_clkgen, reg3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 			(params->frac_phase << 11) | (params->frac_wf_f << 10), 0x3c00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int axi_clkgen_set_rate(struct clk_hw *clk_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	unsigned long rate, unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	unsigned int d, m, dout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	struct axi_clkgen_div_params params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	uint32_t power = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	uint32_t filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	uint32_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	if (parent_rate == 0 || rate == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	axi_clkgen_calc_params(parent_rate, rate, &d, &m, &dout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	if (d == 0 || dout == 0 || m == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	if ((dout & 0x7) != 0 || (m & 0x7) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		power |= 0x9800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_POWER, power, 0x9800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	filter = axi_clkgen_lookup_filter(m - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	lock = axi_clkgen_lookup_lock(m - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	axi_clkgen_calc_clk_params(dout >> 3, dout & 0x7, &params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	axi_clkgen_set_div(axi_clkgen,  MMCM_REG_CLKOUT0_1, MMCM_REG_CLKOUT0_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		MMCM_REG_CLKOUT5_2, &params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	axi_clkgen_calc_clk_params(d, 0, &params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		(params.edge << 13) | (params.nocount << 12) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		(params.high << 6) | params.low, 0x3fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	axi_clkgen_calc_clk_params(m >> 3, m & 0x7, &params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	axi_clkgen_set_div(axi_clkgen,  MMCM_REG_CLK_FB1, MMCM_REG_CLK_FB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		MMCM_REG_CLKOUT6_2, &params);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK1, lock & 0x3ff, 0x3ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		(((lock >> 16) & 0x1f) << 10) | 0x1, 0x7fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		(((lock >> 24) & 0x1f) << 10) | 0x3e9, 0x7fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER1, filter >> 16, 0x9900);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER2, filter, 0x9900);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static long axi_clkgen_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	unsigned int d, m, dout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	unsigned long long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	axi_clkgen_calc_params(*parent_rate, rate, &d, &m, &dout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	if (d == 0 || dout == 0 || m == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	tmp = (unsigned long long)*parent_rate * m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	return min_t(unsigned long long, tmp, LONG_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static unsigned int axi_clkgen_get_div(struct axi_clkgen *axi_clkgen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	unsigned int reg1, unsigned int reg2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	unsigned int val1, val2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	unsigned int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	axi_clkgen_mmcm_read(axi_clkgen, reg2, &val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	if (val2 & MMCM_CLKOUT_NOCOUNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		return 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	axi_clkgen_mmcm_read(axi_clkgen, reg1, &val1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	div = (val1 & 0x3f) + ((val1 >> 6) & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	div <<= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	if (val2 & MMCM_CLK_DIV_DIVIDE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		if ((val2 & BIT(7)) && (val2 & 0x7000) != 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 			div += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 			div += 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		div += (val2 >> 12) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	return div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	unsigned int d, m, dout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	unsigned long long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	dout = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLKOUT0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		MMCM_REG_CLKOUT0_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	m = axi_clkgen_get_div(axi_clkgen, MMCM_REG_CLK_FB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		MMCM_REG_CLK_FB2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_DIV, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	if (val & MMCM_CLK_DIV_NOCOUNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		d = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		d = (val & 0x3f) + ((val >> 6) & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	if (d == 0 || dout == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	tmp = (unsigned long long)parent_rate * m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	tmp = DIV_ROUND_CLOSEST_ULL(tmp, dout * d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	return min_t(unsigned long long, tmp, ULONG_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int axi_clkgen_enable(struct clk_hw *clk_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	axi_clkgen_mmcm_enable(axi_clkgen, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static void axi_clkgen_disable(struct clk_hw *clk_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	axi_clkgen_mmcm_enable(axi_clkgen, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static int axi_clkgen_set_parent(struct clk_hw *clk_hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_CLKSEL, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static u8 axi_clkgen_get_parent(struct clk_hw *clk_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	unsigned int parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_CLKSEL, &parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	return parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static const struct clk_ops axi_clkgen_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	.recalc_rate = axi_clkgen_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	.round_rate = axi_clkgen_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	.set_rate = axi_clkgen_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	.enable = axi_clkgen_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	.disable = axi_clkgen_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	.set_parent = axi_clkgen_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	.get_parent = axi_clkgen_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static const struct of_device_id axi_clkgen_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 		.compatible = "adi,axi-clkgen-2.00.a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) MODULE_DEVICE_TABLE(of, axi_clkgen_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static int axi_clkgen_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	const struct of_device_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	struct axi_clkgen *axi_clkgen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 	struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	const char *parent_names[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	const char *clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	struct resource *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	if (!pdev->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	id = of_match_node(axi_clkgen_ids, pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	if (!id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	axi_clkgen = devm_kzalloc(&pdev->dev, sizeof(*axi_clkgen), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	if (!axi_clkgen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	axi_clkgen->base = devm_ioremap_resource(&pdev->dev, mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	if (IS_ERR(axi_clkgen->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 		return PTR_ERR(axi_clkgen->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	init.num_parents = of_clk_get_parent_count(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	if (init.num_parents < 1 || init.num_parents > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	for (i = 0; i < init.num_parents; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 		parent_names[i] = of_clk_get_parent_name(pdev->dev.of_node, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 		if (!parent_names[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	clk_name = pdev->dev.of_node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	of_property_read_string(pdev->dev.of_node, "clock-output-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 		&clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	init.name = clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	init.ops = &axi_clkgen_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	axi_clkgen_mmcm_enable(axi_clkgen, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	axi_clkgen->clk_hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	ret = devm_clk_hw_register(&pdev->dev, &axi_clkgen->clk_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	return of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_simple_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 				      &axi_clkgen->clk_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static int axi_clkgen_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	of_clk_del_provider(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static struct platform_driver axi_clkgen_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 		.name = "adi-axi-clkgen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 		.of_match_table = axi_clkgen_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	.probe = axi_clkgen_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 	.remove = axi_clkgen_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) module_platform_driver(axi_clkgen_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) MODULE_DESCRIPTION("Driver for the Analog Devices' AXI clkgen pcore clock generator");