^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright IBM Corp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright ASPEED Technology
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define pr_fmt(fmt) "clk-ast2600: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <dt-bindings/clock/ast2600-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "clk-aspeed.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ASPEED_G6_NUM_CLKS 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ASPEED_G6_SILICON_REV 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CHIP_REVISION_ID GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ASPEED_G6_RESET_CTRL 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ASPEED_G6_RESET_CTRL2 0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ASPEED_G6_CLK_STOP_CTRL 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ASPEED_G6_CLK_STOP_CTRL2 0x090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ASPEED_G6_MISC_CTRL 0x0C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define UART_DIV13_EN BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ASPEED_G6_CLK_SELECTION1 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ASPEED_G6_CLK_SELECTION2 0x304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ASPEED_G6_CLK_SELECTION4 0x310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ASPEED_HPLL_PARAM 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ASPEED_APLL_PARAM 0x210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ASPEED_MPLL_PARAM 0x220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ASPEED_EPLL_PARAM 0x240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ASPEED_DPLL_PARAM 0x260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ASPEED_G6_STRAP1 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ASPEED_MAC12_CLK_DLY 0x340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ASPEED_MAC34_CLK_DLY 0x350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Globally visible clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static DEFINE_SPINLOCK(aspeed_g6_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Keeps track of all clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static struct clk_hw_onecell_data *aspeed_g6_clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static void __iomem *scu_g6_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* AST2600 revision: A0, A1, A2, etc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static u8 soc_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Clocks marked with CLK_IS_CRITICAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * ref0 and ref1 are essential for the SoC to operate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * mpll is required if SDRAM is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static const struct aspeed_gate_data aspeed_g6_gates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* clk rst name parent flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) [ASPEED_CLK_GATE_MCLK] = { 0, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) [ASPEED_CLK_GATE_ECLK] = { 1, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) [ASPEED_CLK_GATE_GCLK] = { 2, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* vclk parent - dclk/d1clk/hclk/mclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) [ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) [ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* From dpll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) [ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) [ASPEED_CLK_GATE_REF0CLK] = { 6, -1, "ref0clk-gate", "clkin", CLK_IS_CRITICAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) [ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Reserved 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) [ASPEED_CLK_GATE_USBUHCICLK] = { 9, 15, "usb-uhci-gate", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* From dpll/epll/40mhz usb p1 phy/gpioc6/dp phy pll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) [ASPEED_CLK_GATE_D1CLK] = { 10, 13, "d1clk-gate", "d1clk", 0 }, /* GFX CRT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Reserved 11/12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) [ASPEED_CLK_GATE_YCLK] = { 13, 4, "yclk-gate", NULL, 0 }, /* HAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) [ASPEED_CLK_GATE_USBPORT1CLK] = { 14, 14, "usb-port1-gate", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) [ASPEED_CLK_GATE_UART5CLK] = { 15, -1, "uart5clk-gate", "uart", 0 }, /* UART5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* Reserved 16/19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) [ASPEED_CLK_GATE_MAC1CLK] = { 20, 11, "mac1clk-gate", "mac12", 0 }, /* MAC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) [ASPEED_CLK_GATE_MAC2CLK] = { 21, 12, "mac2clk-gate", "mac12", 0 }, /* MAC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Reserved 22/23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) [ASPEED_CLK_GATE_RSACLK] = { 24, 4, "rsaclk-gate", NULL, 0 }, /* HAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) [ASPEED_CLK_GATE_RVASCLK] = { 25, 9, "rvasclk-gate", NULL, 0 }, /* RVAS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Reserved 26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) [ASPEED_CLK_GATE_EMMCCLK] = { 27, 16, "emmcclk-gate", NULL, 0 }, /* For card clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Reserved 28/29/30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) [ASPEED_CLK_GATE_LCLK] = { 32, 32, "lclk-gate", NULL, 0 }, /* LPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) [ASPEED_CLK_GATE_ESPICLK] = { 33, -1, "espiclk-gate", NULL, 0 }, /* eSPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) [ASPEED_CLK_GATE_REF1CLK] = { 34, -1, "ref1clk-gate", "clkin", CLK_IS_CRITICAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Reserved 35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) [ASPEED_CLK_GATE_SDCLK] = { 36, 56, "sdclk-gate", NULL, 0 }, /* SDIO/SD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) [ASPEED_CLK_GATE_LHCCLK] = { 37, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Reserved 38 RSA: no longer used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Reserved 39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) [ASPEED_CLK_GATE_I3C0CLK] = { 40, 40, "i3c0clk-gate", NULL, 0 }, /* I3C0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) [ASPEED_CLK_GATE_I3C1CLK] = { 41, 41, "i3c1clk-gate", NULL, 0 }, /* I3C1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) [ASPEED_CLK_GATE_I3C2CLK] = { 42, 42, "i3c2clk-gate", NULL, 0 }, /* I3C2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) [ASPEED_CLK_GATE_I3C3CLK] = { 43, 43, "i3c3clk-gate", NULL, 0 }, /* I3C3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) [ASPEED_CLK_GATE_I3C4CLK] = { 44, 44, "i3c4clk-gate", NULL, 0 }, /* I3C4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) [ASPEED_CLK_GATE_I3C5CLK] = { 45, 45, "i3c5clk-gate", NULL, 0 }, /* I3C5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) [ASPEED_CLK_GATE_I3C6CLK] = { 46, 46, "i3c6clk-gate", NULL, 0 }, /* I3C6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) [ASPEED_CLK_GATE_I3C7CLK] = { 47, 47, "i3c7clk-gate", NULL, 0 }, /* I3C7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) [ASPEED_CLK_GATE_UART1CLK] = { 48, -1, "uart1clk-gate", "uart", 0 }, /* UART1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) [ASPEED_CLK_GATE_UART2CLK] = { 49, -1, "uart2clk-gate", "uart", 0 }, /* UART2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) [ASPEED_CLK_GATE_UART3CLK] = { 50, -1, "uart3clk-gate", "uart", 0 }, /* UART3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) [ASPEED_CLK_GATE_UART4CLK] = { 51, -1, "uart4clk-gate", "uart", 0 }, /* UART4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) [ASPEED_CLK_GATE_MAC3CLK] = { 52, 52, "mac3clk-gate", "mac34", 0 }, /* MAC3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) [ASPEED_CLK_GATE_MAC4CLK] = { 53, 53, "mac4clk-gate", "mac34", 0 }, /* MAC4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) [ASPEED_CLK_GATE_UART6CLK] = { 54, -1, "uart6clk-gate", "uartx", 0 }, /* UART6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) [ASPEED_CLK_GATE_UART7CLK] = { 55, -1, "uart7clk-gate", "uartx", 0 }, /* UART7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) [ASPEED_CLK_GATE_UART8CLK] = { 56, -1, "uart8clk-gate", "uartx", 0 }, /* UART8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) [ASPEED_CLK_GATE_UART9CLK] = { 57, -1, "uart9clk-gate", "uartx", 0 }, /* UART9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) [ASPEED_CLK_GATE_UART10CLK] = { 58, -1, "uart10clk-gate", "uartx", 0 }, /* UART10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) [ASPEED_CLK_GATE_UART11CLK] = { 59, -1, "uart11clk-gate", "uartx", 0 }, /* UART11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) [ASPEED_CLK_GATE_UART12CLK] = { 60, -1, "uart12clk-gate", "uartx", 0 }, /* UART12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) [ASPEED_CLK_GATE_UART13CLK] = { 61, -1, "uart13clk-gate", "uartx", 0 }, /* UART13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) [ASPEED_CLK_GATE_FSICLK] = { 62, 59, "fsiclk-gate", NULL, 0 }, /* FSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const struct clk_div_table ast2600_eclk_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { 0x0, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { 0x1, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { 0x2, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { 0x3, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { 0x4, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { 0x5, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { 0x6, 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { 0x7, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const struct clk_div_table ast2600_emmc_extclk_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { 0x0, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { 0x1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { 0x2, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { 0x3, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { 0x4, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { 0x5, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { 0x6, 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { 0x7, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const struct clk_div_table ast2600_mac_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { 0x0, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { 0x1, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { 0x2, 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { 0x3, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { 0x4, 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { 0x5, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { 0x6, 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { 0x7, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const struct clk_div_table ast2600_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { 0x0, 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { 0x1, 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { 0x2, 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { 0x3, 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { 0x4, 20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { 0x5, 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { 0x6, 28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { 0x7, 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* For hpll/dpll/epll/mpll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static struct clk_hw *ast2600_calc_pll(const char *name, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned int mult, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (val & BIT(24)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Pass through mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) mult = div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* F = 25Mhz * [(M + 2) / (n + 1)] / (p + 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u32 m = val & 0x1fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 n = (val >> 13) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 p = (val >> 19) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) mult = (m + 1) / (n + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) div = (p + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) mult, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static struct clk_hw *ast2600_calc_apll(const char *name, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned int mult, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (soc_rev >= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (val & BIT(24)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Pass through mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) mult = div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* F = 25Mhz * [(m + 1) / (n + 1)] / (p + 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u32 m = val & 0x1fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 n = (val >> 13) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 p = (val >> 19) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) mult = (m + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) div = (n + 1) * (p + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (val & BIT(20)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* Pass through mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) mult = div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* F = 25Mhz * (2-od) * [(m + 2) / (n + 1)] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 m = (val >> 5) & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 od = (val >> 4) & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u32 n = val & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) mult = (2 - od) * (m + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) div = n + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return clk_hw_register_fixed_factor(NULL, name, "clkin", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) mult, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static u32 get_bit(u8 idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return BIT(idx % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static u32 get_reset_reg(struct aspeed_clk_gate *gate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (gate->reset_idx < 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return ASPEED_G6_RESET_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return ASPEED_G6_RESET_CTRL2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static u32 get_clock_reg(struct aspeed_clk_gate *gate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (gate->clock_idx < 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return ASPEED_G6_CLK_STOP_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return ASPEED_G6_CLK_STOP_CTRL2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int aspeed_g6_clk_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u32 clk = get_bit(gate->clock_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u32 rst = get_bit(gate->reset_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u32 enval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * If the IP is in reset, treat the clock as not enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * this happens with some clocks such as the USB one when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * coming from cold reset. Without this, aspeed_clk_enable()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * will fail to lift the reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (gate->reset_idx >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) regmap_read(gate->map, get_reset_reg(gate), ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (reg & rst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) regmap_read(gate->map, get_clock_reg(gate), ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return ((reg & clk) == enval) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static int aspeed_g6_clk_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u32 clk = get_bit(gate->clock_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u32 rst = get_bit(gate->reset_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) spin_lock_irqsave(gate->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (aspeed_g6_clk_is_enabled(hw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) spin_unlock_irqrestore(gate->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (gate->reset_idx >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* Put IP in reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) regmap_write(gate->map, get_reset_reg(gate), rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* Delay 100us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* Enable clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (gate->flags & CLK_GATE_SET_TO_DISABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* Clock is clear to enable, so use set to clear register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) regmap_write(gate->map, get_clock_reg(gate) + 0x04, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Clock is set to enable, so use write to set register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) regmap_write(gate->map, get_clock_reg(gate), clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (gate->reset_idx >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* A delay of 10ms is specified by the ASPEED docs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* Take IP out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) regmap_write(gate->map, get_reset_reg(gate) + 0x4, rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) spin_unlock_irqrestore(gate->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static void aspeed_g6_clk_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 clk = get_bit(gate->clock_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) spin_lock_irqsave(gate->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (gate->flags & CLK_GATE_SET_TO_DISABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) regmap_write(gate->map, get_clock_reg(gate), clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* Use set to clear register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) regmap_write(gate->map, get_clock_reg(gate) + 0x4, clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) spin_unlock_irqrestore(gate->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static const struct clk_ops aspeed_g6_clk_gate_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .enable = aspeed_g6_clk_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .disable = aspeed_g6_clk_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .is_enabled = aspeed_g6_clk_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int aspeed_g6_reset_deassert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct aspeed_reset *ar = to_aspeed_reset(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u32 rst = get_bit(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* Use set to clear register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return regmap_write(ar->map, reg + 0x04, rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int aspeed_g6_reset_assert(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct aspeed_reset *ar = to_aspeed_reset(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u32 rst = get_bit(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return regmap_write(ar->map, reg, rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static int aspeed_g6_reset_status(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct aspeed_reset *ar = to_aspeed_reset(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u32 rst = get_bit(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u32 reg = id >= 32 ? ASPEED_G6_RESET_CTRL2 : ASPEED_G6_RESET_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ret = regmap_read(ar->map, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return !!(val & rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static const struct reset_control_ops aspeed_g6_reset_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .assert = aspeed_g6_reset_assert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .deassert = aspeed_g6_reset_deassert,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .status = aspeed_g6_reset_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static struct clk_hw *aspeed_g6_clk_hw_register_gate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) const char *name, const char *parent_name, unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct regmap *map, u8 clock_idx, u8 reset_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) u8 clk_gate_flags, spinlock_t *lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct aspeed_clk_gate *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) gate = kzalloc(sizeof(*gate), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (!gate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) init.ops = &aspeed_g6_clk_gate_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) init.parent_names = parent_name ? &parent_name : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) init.num_parents = parent_name ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) gate->map = map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) gate->clock_idx = clock_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) gate->reset_idx = reset_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) gate->flags = clk_gate_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) gate->lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) gate->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) hw = &gate->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ret = clk_hw_register(dev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) kfree(gate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static const char *const emmc_extclk_parent_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) "emmc_extclk_hpll_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) "mpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static const char * const vclk_parent_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) "dpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) "d1pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) "hclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) "mclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static const char * const d1clk_parent_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) "dpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) "epll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) "usb-phy-40m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) "gpioc6_clkin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) "dp_phy_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int aspeed_g6_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct aspeed_reset *ar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u32 val, rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) map = syscon_node_to_regmap(dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (IS_ERR(map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dev_err(dev, "no syscon regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return PTR_ERR(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (!ar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ar->map = map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ar->rcdev.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) ar->rcdev.nr_resets = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ar->rcdev.ops = &aspeed_g6_reset_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ar->rcdev.of_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ret = devm_reset_controller_register(dev, &ar->rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) dev_err(dev, "could not register reset controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* UART clock div13 setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) regmap_read(map, ASPEED_G6_MISC_CTRL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (val & UART_DIV13_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) rate = 24000000 / 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) rate = 24000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) hw = clk_hw_register_fixed_rate(dev, "uart", NULL, 0, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) aspeed_g6_clk_data->hws[ASPEED_CLK_UART] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* UART6~13 clock div13 setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) regmap_read(map, 0x80, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (val & BIT(31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) rate = 24000000 / 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) rate = 24000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) hw = clk_hw_register_fixed_rate(dev, "uartx", NULL, 0, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) aspeed_g6_clk_data->hws[ASPEED_CLK_UARTX] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* EMMC ext clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) hw = clk_hw_register_fixed_factor(dev, "emmc_extclk_hpll_in", "hpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 0, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) hw = clk_hw_register_mux(dev, "emmc_extclk_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) emmc_extclk_parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ARRAY_SIZE(emmc_extclk_parent_names), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) scu_g6_base + ASPEED_G6_CLK_SELECTION1, 11, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 0, &aspeed_g6_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) hw = clk_hw_register_gate(dev, "emmc_extclk_gate", "emmc_extclk_mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 0, scu_g6_base + ASPEED_G6_CLK_SELECTION1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 15, 0, &aspeed_g6_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) hw = clk_hw_register_divider_table(dev, "emmc_extclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) "emmc_extclk_gate", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) scu_g6_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ASPEED_G6_CLK_SELECTION1, 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 3, 0, ast2600_emmc_extclk_div_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) &aspeed_g6_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) aspeed_g6_clk_data->hws[ASPEED_CLK_EMMC] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* SD/SDIO clock divider and gate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) hw = clk_hw_register_gate(dev, "sd_extclk_gate", "hpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) scu_g6_base + ASPEED_G6_CLK_SELECTION4, 31, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) &aspeed_g6_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) hw = clk_hw_register_divider_table(dev, "sd_extclk", "sd_extclk_gate",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 0, scu_g6_base + ASPEED_G6_CLK_SELECTION4, 28, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ast2600_div_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) &aspeed_g6_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) aspeed_g6_clk_data->hws[ASPEED_CLK_SDIO] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* MAC1/2 RMII 50MHz RCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) hw = clk_hw_register_fixed_rate(dev, "mac12rclk", "hpll", 0, 50000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* MAC1/2 AHB bus clock divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) hw = clk_hw_register_divider_table(dev, "mac12", "hpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) scu_g6_base + ASPEED_G6_CLK_SELECTION1, 16, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ast2600_mac_div_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) &aspeed_g6_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) aspeed_g6_clk_data->hws[ASPEED_CLK_MAC12] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* RMII1 50MHz (RCLK) output enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) hw = clk_hw_register_gate(dev, "mac1rclk", "mac12rclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) scu_g6_base + ASPEED_MAC12_CLK_DLY, 29, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) &aspeed_g6_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) aspeed_g6_clk_data->hws[ASPEED_CLK_MAC1RCLK] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* RMII2 50MHz (RCLK) output enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) hw = clk_hw_register_gate(dev, "mac2rclk", "mac12rclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) scu_g6_base + ASPEED_MAC12_CLK_DLY, 30, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) &aspeed_g6_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) aspeed_g6_clk_data->hws[ASPEED_CLK_MAC2RCLK] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* MAC1/2 RMII 50MHz RCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) hw = clk_hw_register_fixed_rate(dev, "mac34rclk", "hclk", 0, 50000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* MAC3/4 AHB bus clock divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) hw = clk_hw_register_divider_table(dev, "mac34", "hpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) scu_g6_base + 0x310, 24, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ast2600_mac_div_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) &aspeed_g6_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) aspeed_g6_clk_data->hws[ASPEED_CLK_MAC34] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* RMII3 50MHz (RCLK) output enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) hw = clk_hw_register_gate(dev, "mac3rclk", "mac34rclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) scu_g6_base + ASPEED_MAC34_CLK_DLY, 29, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) &aspeed_g6_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) aspeed_g6_clk_data->hws[ASPEED_CLK_MAC3RCLK] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* RMII4 50MHz (RCLK) output enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) hw = clk_hw_register_gate(dev, "mac4rclk", "mac34rclk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) scu_g6_base + ASPEED_MAC34_CLK_DLY, 30, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) &aspeed_g6_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) aspeed_g6_clk_data->hws[ASPEED_CLK_MAC4RCLK] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* LPC Host (LHCLK) clock divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) hw = clk_hw_register_divider_table(dev, "lhclk", "hpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ast2600_div_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) &aspeed_g6_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) aspeed_g6_clk_data->hws[ASPEED_CLK_LHCLK] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* gfx d1clk : use dp clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) regmap_update_bits(map, ASPEED_G6_CLK_SELECTION1, GENMASK(10, 8), BIT(10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* SoC Display clock selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) hw = clk_hw_register_mux(dev, "d1clk", d1clk_parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) ARRAY_SIZE(d1clk_parent_names), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) scu_g6_base + ASPEED_G6_CLK_SELECTION1, 8, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) &aspeed_g6_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) aspeed_g6_clk_data->hws[ASPEED_CLK_D1CLK] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* d1 clk div 0x308[17:15] x [14:12] - 8,7,6,5,4,3,2,1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) regmap_write(map, 0x308, 0x12000); /* 3x3 = 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* P-Bus (BCLK) clock divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) hw = clk_hw_register_divider_table(dev, "bclk", "hpll", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) scu_g6_base + ASPEED_G6_CLK_SELECTION1, 20, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ast2600_div_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) &aspeed_g6_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) aspeed_g6_clk_data->hws[ASPEED_CLK_BCLK] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* Video Capture clock selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) hw = clk_hw_register_mux(dev, "vclk", vclk_parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) ARRAY_SIZE(vclk_parent_names), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) scu_g6_base + ASPEED_G6_CLK_SELECTION2, 12, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) &aspeed_g6_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) aspeed_g6_clk_data->hws[ASPEED_CLK_VCLK] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /* Video Engine clock divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) hw = clk_hw_register_divider_table(dev, "eclk", NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) scu_g6_base + ASPEED_G6_CLK_SELECTION1, 28, 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ast2600_eclk_div_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) &aspeed_g6_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) aspeed_g6_clk_data->hws[ASPEED_CLK_ECLK] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) for (i = 0; i < ARRAY_SIZE(aspeed_g6_gates); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) const struct aspeed_gate_data *gd = &aspeed_g6_gates[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) u32 gate_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * Special case: the USB port 1 clock (bit 14) is always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * working the opposite way from the other ones.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) gate_flags = (gd->clock_idx == 14) ? 0 : CLK_GATE_SET_TO_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) hw = aspeed_g6_clk_hw_register_gate(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) gd->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) gd->parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) gd->flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) gd->clock_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) gd->reset_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) gate_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) &aspeed_g6_clk_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return PTR_ERR(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) aspeed_g6_clk_data->hws[i] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static const struct of_device_id aspeed_g6_clk_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) { .compatible = "aspeed,ast2600-scu" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static struct platform_driver aspeed_g6_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .probe = aspeed_g6_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .name = "ast2600-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .of_match_table = aspeed_g6_clk_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .suppress_bind_attrs = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) builtin_platform_driver(aspeed_g6_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static const u32 ast2600_a0_axi_ahb_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) 2, 2, 3, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static const u32 ast2600_a1_axi_ahb_div0_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) 3, 2, 3, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static const u32 ast2600_a1_axi_ahb_div1_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) 3, 4, 6, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static const u32 ast2600_a1_axi_ahb200_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) 3, 4, 3, 4, 2, 2, 2, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static void __init aspeed_g6_cc(struct regmap *map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) u32 val, div, divbits, axi_div, ahb_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, 25000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * High-speed PLL clock derived from the crystal. This the CPU clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * and we assume that it is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) regmap_read(map, ASPEED_HPLL_PARAM, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) aspeed_g6_clk_data->hws[ASPEED_CLK_HPLL] = ast2600_calc_pll("hpll", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) regmap_read(map, ASPEED_MPLL_PARAM, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) aspeed_g6_clk_data->hws[ASPEED_CLK_MPLL] = ast2600_calc_pll("mpll", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) regmap_read(map, ASPEED_DPLL_PARAM, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) aspeed_g6_clk_data->hws[ASPEED_CLK_DPLL] = ast2600_calc_pll("dpll", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) regmap_read(map, ASPEED_EPLL_PARAM, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) aspeed_g6_clk_data->hws[ASPEED_CLK_EPLL] = ast2600_calc_pll("epll", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) regmap_read(map, ASPEED_APLL_PARAM, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) aspeed_g6_clk_data->hws[ASPEED_CLK_APLL] = ast2600_calc_apll("apll", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* Strap bits 12:11 define the AXI/AHB clock frequency ratio (aka HCLK)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) regmap_read(map, ASPEED_G6_STRAP1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (val & BIT(16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) axi_div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) axi_div = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) divbits = (val >> 11) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (soc_rev >= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (!divbits) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) ahb_div = ast2600_a1_axi_ahb200_tbl[(val >> 8) & 0x3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (val & BIT(16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) ahb_div *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (val & BIT(16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) ahb_div = ast2600_a1_axi_ahb_div1_tbl[divbits];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) ahb_div = ast2600_a1_axi_ahb_div0_tbl[divbits];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) ahb_div = ast2600_a0_axi_ahb_div_table[(val >> 11) & 0x3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, axi_div * ahb_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) aspeed_g6_clk_data->hws[ASPEED_CLK_AHB] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) regmap_read(map, ASPEED_G6_CLK_SELECTION1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) val = (val >> 23) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) div = 4 * (val + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) hw = clk_hw_register_fixed_factor(NULL, "apb1", "hpll", 0, 1, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) aspeed_g6_clk_data->hws[ASPEED_CLK_APB1] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) regmap_read(map, ASPEED_G6_CLK_SELECTION4, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) val = (val >> 9) & 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) div = 2 * (val + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) hw = clk_hw_register_fixed_factor(NULL, "apb2", "ahb", 0, 1, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) aspeed_g6_clk_data->hws[ASPEED_CLK_APB2] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* USB 2.0 port1 phy 40MHz clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) hw = clk_hw_register_fixed_rate(NULL, "usb-phy-40m", NULL, 0, 40000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) aspeed_g6_clk_data->hws[ASPEED_CLK_USBPHY_40M] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static void __init aspeed_g6_cc_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) scu_g6_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (!scu_g6_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) soc_rev = (readl(scu_g6_base + ASPEED_G6_SILICON_REV) & CHIP_REVISION_ID) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) aspeed_g6_clk_data = kzalloc(struct_size(aspeed_g6_clk_data, hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ASPEED_G6_NUM_CLKS), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (!aspeed_g6_clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * This way all clocks fetched before the platform device probes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) * except those we assign here for early use, will be deferred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) for (i = 0; i < ASPEED_G6_NUM_CLKS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) aspeed_g6_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * We check that the regmap works on this very first access,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * but as this is an MMIO-backed regmap, subsequent regmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * access is not going to fail and we skip error checks from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * this point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) map = syscon_node_to_regmap(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (IS_ERR(map)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) pr_err("no syscon regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) aspeed_g6_cc(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) aspeed_g6_clk_data->num = ASPEED_G6_NUM_CLKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_g6_clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) pr_err("failed to add DT provider: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) CLK_OF_DECLARE_DRIVER(aspeed_cc_g6, "aspeed,ast2600-scu", aspeed_g6_cc_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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