Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Structures used by ASPEED clock drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright 2019 IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct clk_div_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * struct aspeed_gate_data - Aspeed gated clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  * @clock_idx: bit used to gate this clock in the clock register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  * @reset_idx: bit used to reset this IP in the reset register. -1 if no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  *             reset is required when enabling the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  * @name: the clock name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  * @parent_name: the name of the parent clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  * @flags: standard clock framework flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct aspeed_gate_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	u8		clock_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	s8		reset_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	const char	*name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	const char	*parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	unsigned long	flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)  * struct aspeed_clk_gate - Aspeed specific clk_gate structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)  * @hw:		handle between common and hardware-specific interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)  * @reg:	register controlling gate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)  * @clock_idx:	bit used to gate this clock in the clock register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)  * @reset_idx:	bit used to reset this IP in the reset register. -1 if no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)  *		reset is required when enabling the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)  * @flags:	hardware-specific flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)  * @lock:	register lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)  * Some of the clocks in the Aspeed SoC must be put in reset before enabling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)  * This modified version of clk_gate allows an optional reset bit to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)  * specified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct aspeed_clk_gate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	struct clk_hw	hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	struct regmap	*map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	u8		clock_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	s8		reset_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	u8		flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	spinlock_t	*lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)  * struct aspeed_reset - Aspeed reset controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)  * @map: regmap to access the containing system controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)  * @rcdev: reset controller device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct aspeed_reset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	struct regmap			*map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	struct reset_controller_dev	rcdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)  * struct aspeed_clk_soc_data - Aspeed SoC specific divisor information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)  * @div_table: Common divider lookup table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)  * @eclk_div_table: Divider lookup table for ECLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)  * @mac_div_table: Divider lookup table for MAC (Ethernet) clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)  * @calc_pll: Callback to maculate common PLL settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct aspeed_clk_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	const struct clk_div_table *div_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	const struct clk_div_table *eclk_div_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	const struct clk_div_table *mac_div_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	struct clk_hw *(*calc_pll)(const char *name, u32 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };