^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 Marvell Technology Group Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Alexandre Belloni <alexandre.belloni@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <dt-bindings/clock/berlin2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "berlin2-avpll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "berlin2-div.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "berlin2-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define REG_PINMUX0 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define REG_PINMUX1 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define REG_SYSPLLCTL0 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define REG_SYSPLLCTL4 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define REG_MEMPLLCTL0 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define REG_MEMPLLCTL4 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define REG_CPUPLLCTL0 0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define REG_CPUPLLCTL4 0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define REG_AVPLLCTL0 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define REG_AVPLLCTL31 0x00cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define REG_AVPLLCTL62 0x0148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define REG_PLLSTATUS 0x014c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define REG_CLKENABLE 0x0150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define REG_CLKSELECT0 0x0154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define REG_CLKSELECT1 0x0158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define REG_CLKSELECT2 0x015c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define REG_CLKSELECT3 0x0160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define REG_CLKSWITCH0 0x0164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define REG_CLKSWITCH1 0x0168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define REG_RESET_TRIGGER 0x0178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define REG_RESET_STATUS0 0x017c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define REG_RESET_STATUS1 0x0180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define REG_SW_GENERIC0 0x0184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define REG_SW_GENERIC3 0x0190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define REG_PRODUCTID 0x01cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define REG_PRODUCTID_EXT 0x01d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define REG_GFX3DCORE_CLKCTL 0x022c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define REG_GFX3DSYS_CLKCTL 0x0230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define REG_ARC_CLKCTL 0x0234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define REG_VIP_CLKCTL 0x0238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define REG_SDIO0XIN_CLKCTL 0x023c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define REG_SDIO1XIN_CLKCTL 0x0240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define REG_GFX3DEXTRA_CLKCTL 0x0244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define REG_GFX3D_RESET 0x0248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define REG_GC360_CLKCTL 0x024c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define REG_SDIO_DLLMST_CLKCTL 0x0250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * BG2/BG2CD SoCs have the following audio/video I/O units:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * audiohd: HDMI TX audio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * audio0: 7.1ch TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * audio1: 2ch TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * audio2: 2ch RX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * audio3: SPDIF TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * video0: HDMI video
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * video1: Secondary video
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * video2: SD auxiliary video
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * There are no external audio clocks (ACLKI0, ACLKI1) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * only one external video clock (VCLKI0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Currently missing bits and pieces:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * - audio_fast_pll is unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * - audiohd_pll is unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * - video0_pll is unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * - audio[023], audiohd parent pll is assumed to be audio_fast_pll
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MAX_CLKS 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static struct clk_hw_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static DEFINE_SPINLOCK(lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static void __iomem *gbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) REFCLK, VIDEO_EXT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) SYSPLL, MEMPLL, CPUPLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) AVPLL_A1, AVPLL_A2, AVPLL_A3, AVPLL_A4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) AVPLL_A5, AVPLL_A6, AVPLL_A7, AVPLL_A8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) AVPLL_B1, AVPLL_B2, AVPLL_B3, AVPLL_B4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) AVPLL_B5, AVPLL_B6, AVPLL_B7, AVPLL_B8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) AUDIO1_PLL, AUDIO_FAST_PLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) VIDEO0_PLL, VIDEO0_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) VIDEO1_PLL, VIDEO1_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) VIDEO2_PLL, VIDEO2_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const char *clk_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) [REFCLK] = "refclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) [VIDEO_EXT0] = "video_ext0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) [SYSPLL] = "syspll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) [MEMPLL] = "mempll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) [CPUPLL] = "cpupll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) [AVPLL_A1] = "avpll_a1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) [AVPLL_A2] = "avpll_a2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) [AVPLL_A3] = "avpll_a3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) [AVPLL_A4] = "avpll_a4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) [AVPLL_A5] = "avpll_a5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) [AVPLL_A6] = "avpll_a6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) [AVPLL_A7] = "avpll_a7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) [AVPLL_A8] = "avpll_a8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) [AVPLL_B1] = "avpll_b1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) [AVPLL_B2] = "avpll_b2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) [AVPLL_B3] = "avpll_b3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) [AVPLL_B4] = "avpll_b4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) [AVPLL_B5] = "avpll_b5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) [AVPLL_B6] = "avpll_b6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) [AVPLL_B7] = "avpll_b7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) [AVPLL_B8] = "avpll_b8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) [AUDIO1_PLL] = "audio1_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) [AUDIO_FAST_PLL] = "audio_fast_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) [VIDEO0_PLL] = "video0_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) [VIDEO0_IN] = "video0_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) [VIDEO1_PLL] = "video1_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) [VIDEO1_IN] = "video1_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) [VIDEO2_PLL] = "video2_pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) [VIDEO2_IN] = "video2_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const struct berlin2_pll_map bg2_pll_map __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .vcodiv = {10, 15, 20, 25, 30, 40, 50, 60, 80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .mult = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .fbdiv_shift = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .rfdiv_shift = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .divsel_shift = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static const u8 default_parent_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) SYSPLL, AVPLL_B4, AVPLL_A5, AVPLL_B6, AVPLL_B7, SYSPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const struct berlin2_div_data bg2_divs[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .name = "sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .parent_ids = (const u8 []){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) SYSPLL, AVPLL_B4, AVPLL_B5, AVPLL_B6, AVPLL_B7, SYSPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .num_parents = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) BERLIN2_DIV_GATE(REG_CLKENABLE, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) BERLIN2_PLL_SELECT(REG_CLKSELECT0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) BERLIN2_DIV_SELECT(REG_CLKSELECT0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .flags = CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .name = "cpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .parent_ids = (const u8 []){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) CPUPLL, MEMPLL, MEMPLL, MEMPLL, MEMPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .num_parents = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) BERLIN2_PLL_SELECT(REG_CLKSELECT0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) BERLIN2_DIV_SELECT(REG_CLKSELECT0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .div_flags = BERLIN2_DIV_HAS_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .name = "drmfigo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .parent_ids = default_parent_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .num_parents = ARRAY_SIZE(default_parent_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) BERLIN2_DIV_GATE(REG_CLKENABLE, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) BERLIN2_PLL_SELECT(REG_CLKSELECT0, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) BERLIN2_DIV_SELECT(REG_CLKSELECT0, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .name = "cfg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .parent_ids = default_parent_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .num_parents = ARRAY_SIZE(default_parent_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) BERLIN2_DIV_GATE(REG_CLKENABLE, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) BERLIN2_PLL_SELECT(REG_CLKSELECT0, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) BERLIN2_DIV_SELECT(REG_CLKSELECT0, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .name = "gfx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .parent_ids = default_parent_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .num_parents = ARRAY_SIZE(default_parent_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) BERLIN2_DIV_GATE(REG_CLKENABLE, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) BERLIN2_PLL_SELECT(REG_CLKSELECT0, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) BERLIN2_DIV_SELECT(REG_CLKSELECT1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .name = "zsp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .parent_ids = default_parent_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .num_parents = ARRAY_SIZE(default_parent_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) BERLIN2_DIV_GATE(REG_CLKENABLE, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) BERLIN2_PLL_SELECT(REG_CLKSELECT1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) BERLIN2_DIV_SELECT(REG_CLKSELECT1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .name = "perif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .parent_ids = default_parent_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .num_parents = ARRAY_SIZE(default_parent_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) BERLIN2_DIV_GATE(REG_CLKENABLE, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) BERLIN2_PLL_SELECT(REG_CLKSELECT1, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) BERLIN2_DIV_SELECT(REG_CLKSELECT1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .flags = CLK_IGNORE_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .name = "pcube",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .parent_ids = default_parent_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .num_parents = ARRAY_SIZE(default_parent_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) BERLIN2_DIV_GATE(REG_CLKENABLE, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) BERLIN2_PLL_SELECT(REG_CLKSELECT1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) BERLIN2_DIV_SELECT(REG_CLKSELECT1, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .name = "vscope",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .parent_ids = default_parent_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .num_parents = ARRAY_SIZE(default_parent_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) BERLIN2_DIV_GATE(REG_CLKENABLE, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) BERLIN2_PLL_SELECT(REG_CLKSELECT1, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) BERLIN2_DIV_SELECT(REG_CLKSELECT1, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .name = "nfc_ecc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .parent_ids = default_parent_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .num_parents = ARRAY_SIZE(default_parent_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) BERLIN2_DIV_GATE(REG_CLKENABLE, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) BERLIN2_PLL_SELECT(REG_CLKSELECT1, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) BERLIN2_DIV_SELECT(REG_CLKSELECT2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) BERLIN2_PLL_SWITCH(REG_CLKSWITCH1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) BERLIN2_DIV_SWITCH(REG_CLKSWITCH1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .name = "vpp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .parent_ids = default_parent_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .num_parents = ARRAY_SIZE(default_parent_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) BERLIN2_DIV_GATE(REG_CLKENABLE, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) BERLIN2_PLL_SELECT(REG_CLKSELECT2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) BERLIN2_DIV_SELECT(REG_CLKSELECT2, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) BERLIN2_PLL_SWITCH(REG_CLKSWITCH1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) BERLIN2_DIV_SWITCH(REG_CLKSWITCH1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .name = "app",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .parent_ids = default_parent_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .num_parents = ARRAY_SIZE(default_parent_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) BERLIN2_DIV_GATE(REG_CLKENABLE, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) BERLIN2_PLL_SELECT(REG_CLKSELECT2, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) BERLIN2_DIV_SELECT(REG_CLKSELECT2, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) BERLIN2_PLL_SWITCH(REG_CLKSWITCH1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) BERLIN2_DIV_SWITCH(REG_CLKSWITCH1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .name = "audio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .parent_ids = (const u8 []){ AUDIO_FAST_PLL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) BERLIN2_DIV_GATE(REG_CLKENABLE, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) BERLIN2_DIV_SELECT(REG_CLKSELECT2, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) BERLIN2_DIV_SWITCH(REG_CLKSWITCH1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .div_flags = BERLIN2_DIV_HAS_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .name = "audio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .parent_ids = (const u8 []){ AUDIO_FAST_PLL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) BERLIN2_DIV_GATE(REG_CLKENABLE, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) BERLIN2_DIV_SELECT(REG_CLKSELECT2, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) BERLIN2_DIV_SWITCH(REG_CLKSWITCH1, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .div_flags = BERLIN2_DIV_HAS_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .name = "audio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .parent_ids = (const u8 []){ AUDIO_FAST_PLL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) BERLIN2_DIV_GATE(REG_CLKENABLE, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) BERLIN2_DIV_SELECT(REG_CLKSELECT2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) BERLIN2_DIV_SWITCH(REG_CLKSWITCH1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .div_flags = BERLIN2_DIV_HAS_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .name = "audio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .parent_ids = (const u8 []){ AUDIO1_PLL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .num_parents = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) BERLIN2_DIV_GATE(REG_CLKENABLE, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) BERLIN2_DIV_SELECT(REG_CLKSELECT3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) BERLIN2_DIV_SWITCH(REG_CLKSWITCH1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .div_flags = BERLIN2_DIV_HAS_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .name = "gfx3d_core",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .parent_ids = default_parent_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .num_parents = ARRAY_SIZE(default_parent_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) BERLIN2_SINGLE_DIV(REG_GFX3DCORE_CLKCTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .name = "gfx3d_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .parent_ids = default_parent_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .num_parents = ARRAY_SIZE(default_parent_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) BERLIN2_SINGLE_DIV(REG_GFX3DSYS_CLKCTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .name = "arc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .parent_ids = default_parent_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .num_parents = ARRAY_SIZE(default_parent_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) BERLIN2_SINGLE_DIV(REG_ARC_CLKCTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .name = "vip",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .parent_ids = default_parent_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .num_parents = ARRAY_SIZE(default_parent_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) BERLIN2_SINGLE_DIV(REG_VIP_CLKCTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .name = "sdio0xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .parent_ids = default_parent_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .num_parents = ARRAY_SIZE(default_parent_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) BERLIN2_SINGLE_DIV(REG_SDIO0XIN_CLKCTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .name = "sdio1xin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .parent_ids = default_parent_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .num_parents = ARRAY_SIZE(default_parent_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) BERLIN2_SINGLE_DIV(REG_SDIO1XIN_CLKCTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .name = "gfx3d_extra",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .parent_ids = default_parent_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .num_parents = ARRAY_SIZE(default_parent_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) BERLIN2_SINGLE_DIV(REG_GFX3DEXTRA_CLKCTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .name = "gc360",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .parent_ids = default_parent_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .num_parents = ARRAY_SIZE(default_parent_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) BERLIN2_SINGLE_DIV(REG_GC360_CLKCTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .name = "sdio_dllmst",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .parent_ids = default_parent_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .num_parents = ARRAY_SIZE(default_parent_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .map = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) BERLIN2_SINGLE_DIV(REG_SDIO_DLLMST_CLKCTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static const struct berlin2_gate_data bg2_gates[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) { "geth0", "perif", 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) { "geth1", "perif", 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) { "sata", "perif", 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) { "ahbapb", "perif", 10, CLK_IGNORE_UNUSED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) { "usb0", "perif", 11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) { "usb1", "perif", 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) { "pbridge", "perif", 13, CLK_IGNORE_UNUSED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) { "sdio0", "perif", 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) { "sdio1", "perif", 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) { "nfc", "perif", 17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) { "smemc", "perif", 19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) { "audiohd", "audiohd_pll", 26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) { "video0", "video0_in", 27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) { "video1", "video1_in", 28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) { "video2", "video2_in", 29 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static void __init berlin2_clock_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct device_node *parent_np = of_get_parent(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) const char *parent_names[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct clk_hw **hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u8 avpll_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) int n, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) clk_data = kzalloc(struct_size(clk_data, hws, MAX_CLKS), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) clk_data->num = MAX_CLKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) hws = clk_data->hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) gbase = of_iomap(parent_np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (!gbase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* overwrite default clock names with DT provided ones */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) clk = of_clk_get_by_name(np, clk_names[REFCLK]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (!IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) clk_names[REFCLK] = __clk_get_name(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) clk = of_clk_get_by_name(np, clk_names[VIDEO_EXT0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (!IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) clk_names[VIDEO_EXT0] = __clk_get_name(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) clk_put(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* simple register PLLs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) ret = berlin2_pll_register(&bg2_pll_map, gbase + REG_SYSPLLCTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) clk_names[SYSPLL], clk_names[REFCLK], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) goto bg2_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ret = berlin2_pll_register(&bg2_pll_map, gbase + REG_MEMPLLCTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) clk_names[MEMPLL], clk_names[REFCLK], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) goto bg2_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ret = berlin2_pll_register(&bg2_pll_map, gbase + REG_CPUPLLCTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) clk_names[CPUPLL], clk_names[REFCLK], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) goto bg2_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (of_device_is_compatible(np, "marvell,berlin2-global-register"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) avpll_flags |= BERLIN2_AVPLL_SCRAMBLE_QUIRK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* audio/video VCOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) ret = berlin2_avpll_vco_register(gbase + REG_AVPLLCTL0, "avpll_vcoA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) clk_names[REFCLK], avpll_flags, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) goto bg2_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) for (n = 0; n < 8; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) ret = berlin2_avpll_channel_register(gbase + REG_AVPLLCTL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) clk_names[AVPLL_A1 + n], n, "avpll_vcoA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) avpll_flags, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) goto bg2_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ret = berlin2_avpll_vco_register(gbase + REG_AVPLLCTL31, "avpll_vcoB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) clk_names[REFCLK], BERLIN2_AVPLL_BIT_QUIRK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) avpll_flags, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) goto bg2_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) for (n = 0; n < 8; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ret = berlin2_avpll_channel_register(gbase + REG_AVPLLCTL31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) clk_names[AVPLL_B1 + n], n, "avpll_vcoB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) BERLIN2_AVPLL_BIT_QUIRK | avpll_flags, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) goto bg2_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* reference clock bypass switches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) parent_names[0] = clk_names[SYSPLL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) parent_names[1] = clk_names[REFCLK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) hw = clk_hw_register_mux(NULL, "syspll_byp", parent_names, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 0, gbase + REG_CLKSWITCH0, 0, 1, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) goto bg2_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) clk_names[SYSPLL] = clk_hw_get_name(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) parent_names[0] = clk_names[MEMPLL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) parent_names[1] = clk_names[REFCLK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) hw = clk_hw_register_mux(NULL, "mempll_byp", parent_names, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 0, gbase + REG_CLKSWITCH0, 1, 1, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) goto bg2_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) clk_names[MEMPLL] = clk_hw_get_name(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) parent_names[0] = clk_names[CPUPLL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) parent_names[1] = clk_names[REFCLK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) hw = clk_hw_register_mux(NULL, "cpupll_byp", parent_names, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 0, gbase + REG_CLKSWITCH0, 2, 1, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) goto bg2_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) clk_names[CPUPLL] = clk_hw_get_name(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* clock muxes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) parent_names[0] = clk_names[AVPLL_B3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) parent_names[1] = clk_names[AVPLL_A3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) hw = clk_hw_register_mux(NULL, clk_names[AUDIO1_PLL], parent_names, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 0, gbase + REG_CLKSELECT2, 29, 1, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) goto bg2_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) parent_names[0] = clk_names[VIDEO0_PLL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) parent_names[1] = clk_names[VIDEO_EXT0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) hw = clk_hw_register_mux(NULL, clk_names[VIDEO0_IN], parent_names, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 0, gbase + REG_CLKSELECT3, 4, 1, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) goto bg2_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) parent_names[0] = clk_names[VIDEO1_PLL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) parent_names[1] = clk_names[VIDEO_EXT0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) hw = clk_hw_register_mux(NULL, clk_names[VIDEO1_IN], parent_names, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 0, gbase + REG_CLKSELECT3, 6, 1, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) goto bg2_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) parent_names[0] = clk_names[AVPLL_A2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) parent_names[1] = clk_names[AVPLL_B2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) hw = clk_hw_register_mux(NULL, clk_names[VIDEO1_PLL], parent_names, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 0, gbase + REG_CLKSELECT3, 7, 1, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) goto bg2_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) parent_names[0] = clk_names[VIDEO2_PLL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) parent_names[1] = clk_names[VIDEO_EXT0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) hw = clk_hw_register_mux(NULL, clk_names[VIDEO2_IN], parent_names, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 0, gbase + REG_CLKSELECT3, 9, 1, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) goto bg2_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) parent_names[0] = clk_names[AVPLL_B1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) parent_names[1] = clk_names[AVPLL_A5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) hw = clk_hw_register_mux(NULL, clk_names[VIDEO2_PLL], parent_names, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 0, gbase + REG_CLKSELECT3, 10, 1, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) goto bg2_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* clock divider cells */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) for (n = 0; n < ARRAY_SIZE(bg2_divs); n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) const struct berlin2_div_data *dd = &bg2_divs[n];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) for (k = 0; k < dd->num_parents; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) parent_names[k] = clk_names[dd->parent_ids[k]];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) hws[CLKID_SYS + n] = berlin2_div_register(&dd->map, gbase,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) dd->name, dd->div_flags, parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) dd->num_parents, dd->flags, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* clock gate cells */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) for (n = 0; n < ARRAY_SIZE(bg2_gates); n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) const struct berlin2_gate_data *gd = &bg2_gates[n];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) hws[CLKID_GETH0 + n] = clk_hw_register_gate(NULL, gd->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) gd->parent_name, gd->flags, gbase + REG_CLKENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) gd->bit_idx, 0, &lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* twdclk is derived from cpu/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) hws[CLKID_TWD] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) clk_hw_register_fixed_factor(NULL, "twd", "cpu", 0, 1, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* check for errors on leaf clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) for (n = 0; n < MAX_CLKS; n++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (!IS_ERR(hws[n]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) pr_err("%pOF: Unable to register leaf clock %d\n", np, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) goto bg2_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* register clk-provider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) bg2_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) iounmap(gbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) CLK_OF_DECLARE(berlin2_clk, "marvell,berlin2-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) berlin2_clock_setup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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