Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2017 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <dt-bindings/clock/bcm-sr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include "clk-iproc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	.pwr_shift = ps, .iso_shift = is }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define SW_CTRL_VAL(o, s) { .offset = o, .shift = s, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	.p_reset_shift = prs }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	.ki_shift = kis, .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	.ka_shift = kas, .ka_width = kaw }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	.hold_shift = hs, .bypass_shift = bs }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static const struct iproc_pll_ctrl sr_genpll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	.flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		IPROC_CLK_PLL_NEEDS_SW_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	.aon = AON_VAL(0x0, 5, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	.reset = RESET_VAL(0x0, 12, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	.dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	.sw_ctrl = SW_CTRL_VAL(0x10, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	.ndiv_int = REG_VAL(0x10, 20, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	.ndiv_frac = REG_VAL(0x10, 0, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	.pdiv = REG_VAL(0x14, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	.status = REG_VAL(0x30, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) static const struct iproc_clk_ctrl sr_genpll0_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	[BCM_SR_GENPLL0_125M_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		.channel = BCM_SR_GENPLL0_125M_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		.enable = ENABLE_VAL(0x4, 6, 0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		.mdiv = REG_VAL(0x18, 0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	[BCM_SR_GENPLL0_SCR_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		.channel = BCM_SR_GENPLL0_SCR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		.enable = ENABLE_VAL(0x4, 7, 1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		.mdiv = REG_VAL(0x18, 10, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	[BCM_SR_GENPLL0_250M_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		.channel = BCM_SR_GENPLL0_250M_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		.enable = ENABLE_VAL(0x4, 8, 2, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		.mdiv = REG_VAL(0x18, 20, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	[BCM_SR_GENPLL0_PCIE_AXI_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		.channel = BCM_SR_GENPLL0_PCIE_AXI_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		.enable = ENABLE_VAL(0x4, 9, 3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		.mdiv = REG_VAL(0x1c, 0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	[BCM_SR_GENPLL0_PAXC_AXI_X2_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		.channel = BCM_SR_GENPLL0_PAXC_AXI_X2_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		.enable = ENABLE_VAL(0x4, 10, 4, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		.mdiv = REG_VAL(0x1c, 10, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	[BCM_SR_GENPLL0_PAXC_AXI_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		.channel = BCM_SR_GENPLL0_PAXC_AXI_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		.enable = ENABLE_VAL(0x4, 11, 5, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		.mdiv = REG_VAL(0x1c, 20, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static int sr_genpll0_clk_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	iproc_pll_clk_setup(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			    &sr_genpll0, NULL, 0, sr_genpll0_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			    ARRAY_SIZE(sr_genpll0_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static const struct iproc_pll_ctrl sr_genpll2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	.flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		IPROC_CLK_PLL_NEEDS_SW_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	.aon = AON_VAL(0x0, 1, 13, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	.reset = RESET_VAL(0x0, 12, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	.dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	.sw_ctrl = SW_CTRL_VAL(0x10, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	.ndiv_int = REG_VAL(0x10, 20, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	.ndiv_frac = REG_VAL(0x10, 0, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	.pdiv = REG_VAL(0x14, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	.status = REG_VAL(0x30, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const struct iproc_clk_ctrl sr_genpll2_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	[BCM_SR_GENPLL2_NIC_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		.channel = BCM_SR_GENPLL2_NIC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		.enable = ENABLE_VAL(0x4, 6, 0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		.mdiv = REG_VAL(0x18, 0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	[BCM_SR_GENPLL2_TS_500_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		.channel = BCM_SR_GENPLL2_TS_500_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		.enable = ENABLE_VAL(0x4, 7, 1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		.mdiv = REG_VAL(0x18, 10, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	[BCM_SR_GENPLL2_125_NITRO_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		.channel = BCM_SR_GENPLL2_125_NITRO_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		.enable = ENABLE_VAL(0x4, 8, 2, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		.mdiv = REG_VAL(0x18, 20, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	[BCM_SR_GENPLL2_CHIMP_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		.channel = BCM_SR_GENPLL2_CHIMP_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		.enable = ENABLE_VAL(0x4, 9, 3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		.mdiv = REG_VAL(0x1c, 0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	[BCM_SR_GENPLL2_NIC_FLASH_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		.channel = BCM_SR_GENPLL2_NIC_FLASH_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		.enable = ENABLE_VAL(0x4, 10, 4, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		.mdiv = REG_VAL(0x1c, 10, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	[BCM_SR_GENPLL2_FS4_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		.channel = BCM_SR_GENPLL2_FS4_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		.enable = ENABLE_VAL(0x4, 11, 5, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		.mdiv = REG_VAL(0x1c, 20, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int sr_genpll2_clk_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	iproc_pll_clk_setup(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			    &sr_genpll2, NULL, 0, sr_genpll2_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			    ARRAY_SIZE(sr_genpll2_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static const struct iproc_pll_ctrl sr_genpll3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		IPROC_CLK_PLL_NEEDS_SW_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	.aon = AON_VAL(0x0, 1, 19, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	.reset = RESET_VAL(0x0, 12, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	.dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.sw_ctrl = SW_CTRL_VAL(0x10, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	.ndiv_int = REG_VAL(0x10, 20, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	.ndiv_frac = REG_VAL(0x10, 0, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	.pdiv = REG_VAL(0x14, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	.status = REG_VAL(0x30, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const struct iproc_clk_ctrl sr_genpll3_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	[BCM_SR_GENPLL3_HSLS_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		.channel = BCM_SR_GENPLL3_HSLS_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		.enable = ENABLE_VAL(0x4, 6, 0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		.mdiv = REG_VAL(0x18, 0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	[BCM_SR_GENPLL3_SDIO_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		.channel = BCM_SR_GENPLL3_SDIO_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		.enable = ENABLE_VAL(0x4, 7, 1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		.mdiv = REG_VAL(0x18, 10, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static void sr_genpll3_clk_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	iproc_pll_clk_setup(node, &sr_genpll3, NULL, 0, sr_genpll3_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 			    ARRAY_SIZE(sr_genpll3_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) CLK_OF_DECLARE(sr_genpll3_clk, "brcm,sr-genpll3", sr_genpll3_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static const struct iproc_pll_ctrl sr_genpll4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	.flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		IPROC_CLK_PLL_NEEDS_SW_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	.aon = AON_VAL(0x0, 1, 25, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	.reset = RESET_VAL(0x0, 12, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	.dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.sw_ctrl = SW_CTRL_VAL(0x10, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	.ndiv_int = REG_VAL(0x10, 20, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	.ndiv_frac = REG_VAL(0x10, 0, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	.pdiv = REG_VAL(0x14, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	.status = REG_VAL(0x30, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const struct iproc_clk_ctrl sr_genpll4_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	[BCM_SR_GENPLL4_CCN_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		.channel = BCM_SR_GENPLL4_CCN_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		.enable = ENABLE_VAL(0x4, 6, 0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		.mdiv = REG_VAL(0x18, 0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	[BCM_SR_GENPLL4_TPIU_PLL_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		.channel = BCM_SR_GENPLL4_TPIU_PLL_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		.enable = ENABLE_VAL(0x4, 7, 1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		.mdiv = REG_VAL(0x18, 10, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	[BCM_SR_GENPLL4_NOC_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		.channel = BCM_SR_GENPLL4_NOC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		.enable = ENABLE_VAL(0x4, 8, 2, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		.mdiv = REG_VAL(0x18, 20, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	[BCM_SR_GENPLL4_CHCLK_FS4_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		.channel = BCM_SR_GENPLL4_CHCLK_FS4_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		.enable = ENABLE_VAL(0x4, 9, 3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		.mdiv = REG_VAL(0x1c, 0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	[BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		.channel = BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		.enable = ENABLE_VAL(0x4, 10, 4, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		.mdiv = REG_VAL(0x1c, 10, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static int sr_genpll4_clk_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	iproc_pll_clk_setup(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			    &sr_genpll4, NULL, 0, sr_genpll4_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			    ARRAY_SIZE(sr_genpll4_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const struct iproc_pll_ctrl sr_genpll5 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		IPROC_CLK_PLL_NEEDS_SW_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	.aon = AON_VAL(0x0, 1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	.reset = RESET_VAL(0x0, 12, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	.dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.sw_ctrl = SW_CTRL_VAL(0x10, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	.ndiv_int = REG_VAL(0x10, 20, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	.ndiv_frac = REG_VAL(0x10, 0, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	.pdiv = REG_VAL(0x14, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	.status = REG_VAL(0x30, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const struct iproc_clk_ctrl sr_genpll5_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	[BCM_SR_GENPLL5_FS4_HF_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		.channel = BCM_SR_GENPLL5_FS4_HF_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		.enable = ENABLE_VAL(0x4, 6, 0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		.mdiv = REG_VAL(0x18, 0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	[BCM_SR_GENPLL5_CRYPTO_AE_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		.channel = BCM_SR_GENPLL5_CRYPTO_AE_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		.enable = ENABLE_VAL(0x4, 7, 1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		.mdiv = REG_VAL(0x18, 10, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	[BCM_SR_GENPLL5_RAID_AE_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		.channel = BCM_SR_GENPLL5_RAID_AE_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		.enable = ENABLE_VAL(0x4, 8, 2, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		.mdiv = REG_VAL(0x18, 20, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int sr_genpll5_clk_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	iproc_pll_clk_setup(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 			    &sr_genpll5, NULL, 0, sr_genpll5_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			    ARRAY_SIZE(sr_genpll5_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static const struct iproc_pll_ctrl sr_lcpll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	.flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	.aon = AON_VAL(0x0, 2, 19, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	.reset = RESET_VAL(0x0, 31, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	.sw_ctrl = SW_CTRL_VAL(0x4, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	.ndiv_int = REG_VAL(0x4, 16, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	.pdiv = REG_VAL(0x4, 26, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	.status = REG_VAL(0x38, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static const struct iproc_clk_ctrl sr_lcpll0_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	[BCM_SR_LCPLL0_SATA_REFP_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		.channel = BCM_SR_LCPLL0_SATA_REFP_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		.enable = ENABLE_VAL(0x0, 7, 1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		.mdiv = REG_VAL(0x14, 0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	[BCM_SR_LCPLL0_SATA_REFN_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		.channel = BCM_SR_LCPLL0_SATA_REFN_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		.enable = ENABLE_VAL(0x0, 8, 2, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		.mdiv = REG_VAL(0x14, 10, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	[BCM_SR_LCPLL0_SATA_350_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		.channel = BCM_SR_LCPLL0_SATA_350_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		.enable = ENABLE_VAL(0x0, 9, 3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		.mdiv = REG_VAL(0x14, 20, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	[BCM_SR_LCPLL0_SATA_500_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		.channel = BCM_SR_LCPLL0_SATA_500_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		.enable = ENABLE_VAL(0x0, 10, 4, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		.mdiv = REG_VAL(0x18, 0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int sr_lcpll0_clk_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	iproc_pll_clk_setup(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 			    &sr_lcpll0, NULL, 0, sr_lcpll0_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 			    ARRAY_SIZE(sr_lcpll0_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const struct iproc_pll_ctrl sr_lcpll1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	.flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	.aon = AON_VAL(0x0, 2, 22, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	.reset = RESET_VAL(0x0, 31, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	.sw_ctrl = SW_CTRL_VAL(0x4, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	.ndiv_int = REG_VAL(0x4, 16, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	.pdiv = REG_VAL(0x4, 26, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	.status = REG_VAL(0x38, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static const struct iproc_clk_ctrl sr_lcpll1_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	[BCM_SR_LCPLL1_WAN_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		.channel = BCM_SR_LCPLL1_WAN_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		.enable = ENABLE_VAL(0x0, 7, 1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		.mdiv = REG_VAL(0x14, 0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	[BCM_SR_LCPLL1_USB_REF_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		.channel = BCM_SR_LCPLL1_USB_REF_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		.enable = ENABLE_VAL(0x0, 8, 2, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		.mdiv = REG_VAL(0x14, 10, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	[BCM_SR_LCPLL1_CRMU_TS_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		.channel = BCM_SR_LCPLL1_CRMU_TS_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		.enable = ENABLE_VAL(0x0, 9, 3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		.mdiv = REG_VAL(0x14, 20, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static int sr_lcpll1_clk_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	iproc_pll_clk_setup(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 			    &sr_lcpll1, NULL, 0, sr_lcpll1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 			    ARRAY_SIZE(sr_lcpll1_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static const struct iproc_pll_ctrl sr_lcpll_pcie = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	.flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	.aon = AON_VAL(0x0, 2, 25, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	.reset = RESET_VAL(0x0, 31, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	.sw_ctrl = SW_CTRL_VAL(0x4, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	.ndiv_int = REG_VAL(0x4, 16, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	.pdiv = REG_VAL(0x4, 26, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	.status = REG_VAL(0x38, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static const struct iproc_clk_ctrl sr_lcpll_pcie_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	[BCM_SR_LCPLL_PCIE_PHY_REF_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		.channel = BCM_SR_LCPLL_PCIE_PHY_REF_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		.enable = ENABLE_VAL(0x0, 7, 1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		.mdiv = REG_VAL(0x14, 0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) static int sr_lcpll_pcie_clk_init(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	iproc_pll_clk_setup(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 			    &sr_lcpll_pcie, NULL, 0, sr_lcpll_pcie_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 			    ARRAY_SIZE(sr_lcpll_pcie_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static const struct of_device_id sr_clk_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	{ .compatible = "brcm,sr-genpll0", .data = sr_genpll0_clk_init },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	{ .compatible = "brcm,sr-genpll2", .data = sr_genpll2_clk_init },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	{ .compatible = "brcm,sr-genpll4", .data = sr_genpll4_clk_init },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	{ .compatible = "brcm,sr-genpll5", .data = sr_genpll5_clk_init },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	{ .compatible = "brcm,sr-lcpll0", .data = sr_lcpll0_clk_init },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	{ .compatible = "brcm,sr-lcpll1", .data = sr_lcpll1_clk_init },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	{ .compatible = "brcm,sr-lcpll-pcie", .data = sr_lcpll_pcie_clk_init },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static int sr_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	int (*probe_func)(struct platform_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	probe_func = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	if (!probe_func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	return probe_func(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static struct platform_driver sr_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		.name = "sr-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		.of_match_table = sr_clk_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	.probe = sr_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) builtin_platform_driver(sr_clk_driver);