^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2015 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <dt-bindings/clock/bcm-nsp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "clk-iproc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .pwr_shift = ps, .iso_shift = is }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .p_reset_shift = prs }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .ka_width = kaw }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .hold_shift = hs, .bypass_shift = bs }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static void __init nsp_armpll_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) iproc_armpll_setup(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) CLK_OF_DECLARE(nsp_armpll, "brcm,nsp-armpll", nsp_armpll_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static const struct iproc_pll_ctrl genpll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .aon = AON_VAL(0x0, 1, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .reset = RESET_VAL(0x0, 11, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .ndiv_int = REG_VAL(0x14, 20, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .ndiv_frac = REG_VAL(0x14, 0, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .pdiv = REG_VAL(0x18, 24, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .status = REG_VAL(0x20, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static const struct iproc_clk_ctrl genpll_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) [BCM_NSP_GENPLL_PHY_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .channel = BCM_NSP_GENPLL_PHY_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .enable = ENABLE_VAL(0x4, 12, 6, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .mdiv = REG_VAL(0x18, 16, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) [BCM_NSP_GENPLL_ENET_SW_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .channel = BCM_NSP_GENPLL_ENET_SW_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .enable = ENABLE_VAL(0x4, 13, 7, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .mdiv = REG_VAL(0x18, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) [BCM_NSP_GENPLL_USB_PHY_REF_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .channel = BCM_NSP_GENPLL_USB_PHY_REF_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .enable = ENABLE_VAL(0x4, 14, 8, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .mdiv = REG_VAL(0x18, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) [BCM_NSP_GENPLL_IPROCFAST_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .channel = BCM_NSP_GENPLL_IPROCFAST_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .enable = ENABLE_VAL(0x4, 15, 9, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .mdiv = REG_VAL(0x1c, 16, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) [BCM_NSP_GENPLL_SATA1_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .channel = BCM_NSP_GENPLL_SATA1_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .enable = ENABLE_VAL(0x4, 16, 10, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .mdiv = REG_VAL(0x1c, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) [BCM_NSP_GENPLL_SATA2_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .channel = BCM_NSP_GENPLL_SATA2_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .enable = ENABLE_VAL(0x4, 17, 11, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .mdiv = REG_VAL(0x1c, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static void __init nsp_genpll_clk_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) iproc_pll_clk_setup(node, &genpll, NULL, 0, genpll_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ARRAY_SIZE(genpll_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) CLK_OF_DECLARE(nsp_genpll_clk, "brcm,nsp-genpll", nsp_genpll_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const struct iproc_pll_ctrl lcpll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .flags = IPROC_CLK_PLL_HAS_NDIV_FRAC | IPROC_CLK_EMBED_PWRCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .aon = AON_VAL(0x0, 1, 24, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .reset = RESET_VAL(0x0, 23, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .dig_filter = DF_VAL(0x0, 16, 3, 12, 4, 19, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .ndiv_int = REG_VAL(0x4, 20, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .ndiv_frac = REG_VAL(0x4, 0, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .pdiv = REG_VAL(0x4, 28, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .status = REG_VAL(0x10, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static const struct iproc_clk_ctrl lcpll0_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) [BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .channel = BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .enable = ENABLE_VAL(0x0, 6, 3, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .mdiv = REG_VAL(0x8, 24, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) [BCM_NSP_LCPLL0_SDIO_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .channel = BCM_NSP_LCPLL0_SDIO_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .enable = ENABLE_VAL(0x0, 7, 4, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .mdiv = REG_VAL(0x8, 16, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) [BCM_NSP_LCPLL0_DDR_PHY_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .channel = BCM_NSP_LCPLL0_DDR_PHY_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .enable = ENABLE_VAL(0x0, 8, 5, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .mdiv = REG_VAL(0x8, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static void __init nsp_lcpll0_clk_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) iproc_pll_clk_setup(node, &lcpll0, NULL, 0, lcpll0_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ARRAY_SIZE(lcpll0_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) CLK_OF_DECLARE(nsp_lcpll0_clk, "brcm,nsp-lcpll0", nsp_lcpll0_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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