Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Copyright (C) 2015 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <dt-bindings/clock/bcm-ns2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include "clk-iproc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	.pwr_shift = ps, .iso_shift = is }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	.p_reset_shift = prs }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	.ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas,    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	.ka_width = kaw }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	.hold_shift = hs, .bypass_shift = bs }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) static const struct iproc_pll_ctrl genpll_scr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	.flags = IPROC_CLK_AON | IPROC_CLK_PLL_SPLIT_STAT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	.aon = AON_VAL(0x0, 1, 15, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	.reset = RESET_VAL(0x4, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	.dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	.ndiv_int = REG_VAL(0x8, 4, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	.pdiv = REG_VAL(0x8, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	.vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	.status = REG_VAL(0x0, 27, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static const struct iproc_clk_ctrl genpll_scr_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	/* bypass_shift, the last value passed into ENABLE_VAL(), is not defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	 * in NS2.  However, it doesn't appear to be used anywhere, so setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	 * it to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	[BCM_NS2_GENPLL_SCR_SCR_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		.channel = BCM_NS2_GENPLL_SCR_SCR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		.enable = ENABLE_VAL(0x0, 18, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		.mdiv = REG_VAL(0x18, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	[BCM_NS2_GENPLL_SCR_FS_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		.channel = BCM_NS2_GENPLL_SCR_FS_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		.enable = ENABLE_VAL(0x0, 19, 13, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		.mdiv = REG_VAL(0x18, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	[BCM_NS2_GENPLL_SCR_AUDIO_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		.channel = BCM_NS2_GENPLL_SCR_AUDIO_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		.enable = ENABLE_VAL(0x0, 20, 14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		.mdiv = REG_VAL(0x14, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	[BCM_NS2_GENPLL_SCR_CH3_UNUSED] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		.channel = BCM_NS2_GENPLL_SCR_CH3_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		.enable = ENABLE_VAL(0x0, 21, 15, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		.mdiv = REG_VAL(0x14, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	[BCM_NS2_GENPLL_SCR_CH4_UNUSED] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		.channel = BCM_NS2_GENPLL_SCR_CH4_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		.enable = ENABLE_VAL(0x0, 22, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		.mdiv = REG_VAL(0x14, 16, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	[BCM_NS2_GENPLL_SCR_CH5_UNUSED] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		.channel = BCM_NS2_GENPLL_SCR_CH5_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		.enable = ENABLE_VAL(0x0, 23, 17, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		.mdiv = REG_VAL(0x14, 24, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static void __init ns2_genpll_scr_clk_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	iproc_pll_clk_setup(node, &genpll_scr, NULL, 0, genpll_scr_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 			    ARRAY_SIZE(genpll_scr_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) CLK_OF_DECLARE(ns2_genpll_src_clk, "brcm,ns2-genpll-scr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	       ns2_genpll_scr_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const struct iproc_pll_ctrl genpll_sw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	.flags = IPROC_CLK_AON | IPROC_CLK_PLL_SPLIT_STAT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	.aon = AON_VAL(0x0, 1, 11, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	.reset = RESET_VAL(0x4, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	.dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	.ndiv_int = REG_VAL(0x8, 4, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	.pdiv = REG_VAL(0x8, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	.vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	.status = REG_VAL(0x0, 13, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static const struct iproc_clk_ctrl genpll_sw_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	/* bypass_shift, the last value passed into ENABLE_VAL(), is not defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	 * in NS2.  However, it doesn't appear to be used anywhere, so setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	 * it to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	[BCM_NS2_GENPLL_SW_RPE_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		.channel = BCM_NS2_GENPLL_SW_RPE_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		.enable = ENABLE_VAL(0x0, 18, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		.mdiv = REG_VAL(0x18, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	[BCM_NS2_GENPLL_SW_250_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		.channel = BCM_NS2_GENPLL_SW_250_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		.enable = ENABLE_VAL(0x0, 19, 13, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		.mdiv = REG_VAL(0x18, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	[BCM_NS2_GENPLL_SW_NIC_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		.channel = BCM_NS2_GENPLL_SW_NIC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		.enable = ENABLE_VAL(0x0, 20, 14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		.mdiv = REG_VAL(0x14, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	[BCM_NS2_GENPLL_SW_CHIMP_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		.channel = BCM_NS2_GENPLL_SW_CHIMP_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		.enable = ENABLE_VAL(0x0, 21, 15, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		.mdiv = REG_VAL(0x14, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	[BCM_NS2_GENPLL_SW_PORT_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		.channel = BCM_NS2_GENPLL_SW_PORT_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		.enable = ENABLE_VAL(0x0, 22, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		.mdiv = REG_VAL(0x14, 16, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	[BCM_NS2_GENPLL_SW_SDIO_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		.channel = BCM_NS2_GENPLL_SW_SDIO_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		.enable = ENABLE_VAL(0x0, 23, 17, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		.mdiv = REG_VAL(0x14, 24, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static void __init ns2_genpll_sw_clk_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	iproc_pll_clk_setup(node, &genpll_sw, NULL, 0, genpll_sw_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			    ARRAY_SIZE(genpll_sw_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) CLK_OF_DECLARE(ns2_genpll_sw_clk, "brcm,ns2-genpll-sw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	       ns2_genpll_sw_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const struct iproc_pll_ctrl lcpll_ddr = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	.flags = IPROC_CLK_AON | IPROC_CLK_PLL_SPLIT_STAT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	.aon = AON_VAL(0x0, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.reset = RESET_VAL(0x4, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	.dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	.ndiv_int = REG_VAL(0x8, 4, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	.pdiv = REG_VAL(0x8, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	.vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	.status = REG_VAL(0x0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const struct iproc_clk_ctrl lcpll_ddr_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	/* bypass_shift, the last value passed into ENABLE_VAL(), is not defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	 * in NS2.  However, it doesn't appear to be used anywhere, so setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	 * it to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	[BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		.channel = BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		.enable = ENABLE_VAL(0x0, 18, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		.mdiv = REG_VAL(0x14, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	[BCM_NS2_LCPLL_DDR_DDR_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		.channel = BCM_NS2_LCPLL_DDR_DDR_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		.enable = ENABLE_VAL(0x0, 19, 13, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		.mdiv = REG_VAL(0x14, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	[BCM_NS2_LCPLL_DDR_CH2_UNUSED] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		.channel = BCM_NS2_LCPLL_DDR_CH2_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		.enable = ENABLE_VAL(0x0, 20, 14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		.mdiv = REG_VAL(0x10, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	[BCM_NS2_LCPLL_DDR_CH3_UNUSED] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		.channel = BCM_NS2_LCPLL_DDR_CH3_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		.enable = ENABLE_VAL(0x0, 21, 15, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		.mdiv = REG_VAL(0x10, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	[BCM_NS2_LCPLL_DDR_CH4_UNUSED] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		.channel = BCM_NS2_LCPLL_DDR_CH4_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		.enable = ENABLE_VAL(0x0, 22, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		.mdiv = REG_VAL(0x10, 16, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	[BCM_NS2_LCPLL_DDR_CH5_UNUSED] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		.channel = BCM_NS2_LCPLL_DDR_CH5_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		.enable = ENABLE_VAL(0x0, 23, 17, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		.mdiv = REG_VAL(0x10, 24, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static void __init ns2_lcpll_ddr_clk_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	iproc_pll_clk_setup(node, &lcpll_ddr, NULL, 0, lcpll_ddr_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			    ARRAY_SIZE(lcpll_ddr_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) CLK_OF_DECLARE(ns2_lcpll_ddr_clk, "brcm,ns2-lcpll-ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	       ns2_lcpll_ddr_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const struct iproc_pll_ctrl lcpll_ports = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	.flags = IPROC_CLK_AON | IPROC_CLK_PLL_SPLIT_STAT_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	.aon = AON_VAL(0x0, 2, 5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	.reset = RESET_VAL(0x4, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	.dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	.ndiv_int = REG_VAL(0x8, 4, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	.pdiv = REG_VAL(0x8, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	.vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	.status = REG_VAL(0x0, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const struct iproc_clk_ctrl lcpll_ports_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	/* bypass_shift, the last value passed into ENABLE_VAL(), is not defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	 * in NS2.  However, it doesn't appear to be used anywhere, so setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	 * it to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	[BCM_NS2_LCPLL_PORTS_WAN_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		.channel = BCM_NS2_LCPLL_PORTS_WAN_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		.enable = ENABLE_VAL(0x0, 18, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		.mdiv = REG_VAL(0x14, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	[BCM_NS2_LCPLL_PORTS_RGMII_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		.channel = BCM_NS2_LCPLL_PORTS_RGMII_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		.enable = ENABLE_VAL(0x0, 19, 13, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		.mdiv = REG_VAL(0x14, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	[BCM_NS2_LCPLL_PORTS_CH2_UNUSED] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		.channel = BCM_NS2_LCPLL_PORTS_CH2_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		.enable = ENABLE_VAL(0x0, 20, 14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		.mdiv = REG_VAL(0x10, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	[BCM_NS2_LCPLL_PORTS_CH3_UNUSED] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		.channel = BCM_NS2_LCPLL_PORTS_CH3_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		.enable = ENABLE_VAL(0x0, 21, 15, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		.mdiv = REG_VAL(0x10, 8, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	[BCM_NS2_LCPLL_PORTS_CH4_UNUSED] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		.channel = BCM_NS2_LCPLL_PORTS_CH4_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		.enable = ENABLE_VAL(0x0, 22, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		.mdiv = REG_VAL(0x10, 16, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	[BCM_NS2_LCPLL_PORTS_CH5_UNUSED] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		.channel = BCM_NS2_LCPLL_PORTS_CH5_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		.flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		.enable = ENABLE_VAL(0x0, 23, 17, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		.mdiv = REG_VAL(0x10, 24, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static void __init ns2_lcpll_ports_clk_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	iproc_pll_clk_setup(node, &lcpll_ports, NULL, 0, lcpll_ports_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 			    ARRAY_SIZE(lcpll_ports_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) CLK_OF_DECLARE(ns2_lcpll_ports_clk, "brcm,ns2-lcpll-ports",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	       ns2_lcpll_ports_clk_init);