^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2014 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #ifndef _CLK_IPROC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define _CLK_IPROC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IPROC_CLK_NAME_LEN 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IPROC_CLK_INVALID_OFFSET 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define bit_mask(width) ((1 << (width)) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* clocks that should not be disabled at runtime */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IPROC_CLK_AON BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* PLL that requires gating through ASIU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IPROC_CLK_PLL_ASIU BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* PLL that has fractional part of the NDIV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IPROC_CLK_PLL_HAS_NDIV_FRAC BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Some of the iProc PLL/clocks may have an ASIC bug that requires read back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * of the same register following the write to flush the write transaction into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * the intended register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IPROC_CLK_NEEDS_READ_BACK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * Some PLLs require the PLL SW override bit to be set before changes can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * applied to the PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IPROC_CLK_PLL_NEEDS_SW_CFG BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Some PLLs use a different way to control clock power, via the PWRDWN bit in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * the PLL control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IPROC_CLK_EMBED_PWRCTRL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Some PLLs have separate registers for Status and Control. Identify this to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * let the driver know if additional registers need to be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IPROC_CLK_PLL_SPLIT_STAT_CTRL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * Some PLLs have an additional divide by 2 in master clock calculation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * MCLK = VCO_freq / (Mdiv * 2). Identify this to let the driver know
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * of modified calculations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IPROC_CLK_MCLK_DIV_BY_2 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Some PLLs provide a look up table for the leaf clock frequencies and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * auto calculates VCO frequency parameters based on the provided leaf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * clock frequencies. They have a user mode that allows the divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * controls to be determined by the user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IPROC_CLK_PLL_USER_MODE_ON BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * Some PLLs have an active low reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IPROC_CLK_PLL_RESET_ACTIVE_LOW BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * Calculate the PLL parameters are runtime, instead of using table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IPROC_CLK_PLL_CALC_PARAM BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * Parameters for VCO frequency configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * VCO frequency =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * ((ndiv_int + ndiv_frac / 2^20) * (ref freqeuncy / pdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct iproc_pll_vco_param {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int ndiv_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned int ndiv_frac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int pdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct iproc_clk_reg_op {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned int width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * Clock gating control at the top ASIU level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct iproc_asiu_gate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned int en_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * Control of powering on/off of a PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * Before powering off a PLL, input isolation (ISO) needs to be enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct iproc_pll_aon_pwr_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int pwr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned int pwr_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned int iso_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Control of the PLL reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct iproc_pll_reset_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned int reset_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned int p_reset_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * Control of the Ki, Kp, and Ka parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct iproc_pll_dig_filter_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned int ki_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int ki_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned int kp_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned int kp_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned int ka_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned int ka_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * To enable SW control of the PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct iproc_pll_sw_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct iproc_pll_vco_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned int u_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned int l_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * Main PLL control parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct iproc_pll_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct iproc_pll_aon_pwr_ctrl aon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct iproc_asiu_gate asiu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct iproc_pll_reset_ctrl reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct iproc_pll_dig_filter_ctrl dig_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct iproc_pll_sw_ctrl sw_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct iproc_clk_reg_op ndiv_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct iproc_clk_reg_op ndiv_frac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct iproc_clk_reg_op pdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct iproc_pll_vco_ctrl vco_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct iproc_clk_reg_op status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct iproc_clk_reg_op macro_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * Controls enabling/disabling a PLL derived clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct iproc_clk_enable_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned int enable_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsigned int hold_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) unsigned int bypass_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * Main clock control parameters for clocks derived from the PLLs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct iproc_clk_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned int channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct iproc_clk_enable_ctrl enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct iproc_clk_reg_op mdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * Divisor of the ASIU clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct iproc_asiu_div {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned int en_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned int high_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) unsigned int high_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned int low_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned int low_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) void iproc_armpll_setup(struct device_node *node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) void iproc_pll_clk_setup(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) const struct iproc_pll_ctrl *pll_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) const struct iproc_pll_vco_param *vco,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned int num_vco_entries,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) const struct iproc_clk_ctrl *clk_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned int num_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) void iproc_asiu_setup(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) const struct iproc_asiu_div *div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) const struct iproc_asiu_gate *gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned int num_clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #endif /* _CLK_IPROC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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