^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2014 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "clk-iproc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct iproc_asiu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct iproc_asiu_clk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct iproc_asiu *asiu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct iproc_asiu_div div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct iproc_asiu_gate gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct iproc_asiu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) void __iomem *div_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void __iomem *gate_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct clk_hw_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct iproc_asiu_clk *clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define to_asiu_clk(hw) container_of(hw, struct iproc_asiu_clk, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static int iproc_asiu_clk_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct iproc_asiu_clk *clk = to_asiu_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct iproc_asiu *asiu = clk->asiu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* some clocks at the ASIU level are always enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) val = readl(asiu->gate_base + clk->gate.offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) val |= (1 << clk->gate.en_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) writel(val, asiu->gate_base + clk->gate.offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static void iproc_asiu_clk_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct iproc_asiu_clk *clk = to_asiu_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct iproc_asiu *asiu = clk->asiu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* some clocks at the ASIU level are always enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) val = readl(asiu->gate_base + clk->gate.offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) val &= ~(1 << clk->gate.en_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) writel(val, asiu->gate_base + clk->gate.offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static unsigned long iproc_asiu_clk_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct iproc_asiu_clk *clk = to_asiu_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct iproc_asiu *asiu = clk->asiu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned int div_h, div_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (parent_rate == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) clk->rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* if clock divisor is not enabled, simply return parent rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) val = readl(asiu->div_base + clk->div.offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if ((val & (1 << clk->div.en_shift)) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) clk->rate = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* clock rate = parent rate / (high_div + 1) + (low_div + 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) div_h = (val >> clk->div.high_shift) & bit_mask(clk->div.high_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) div_h++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) div_l = (val >> clk->div.low_shift) & bit_mask(clk->div.low_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) div_l++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) clk->rate = parent_rate / (div_h + div_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) pr_debug("%s: rate: %lu. parent rate: %lu div_h: %u div_l: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) __func__, clk->rate, parent_rate, div_h, div_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return clk->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static long iproc_asiu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (rate == 0 || *parent_rate == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (rate == *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return *parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) div = DIV_ROUND_CLOSEST(*parent_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (div < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return *parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return *parent_rate / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int iproc_asiu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct iproc_asiu_clk *clk = to_asiu_clk(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct iproc_asiu *asiu = clk->asiu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned int div, div_h, div_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (rate == 0 || parent_rate == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* simply disable the divisor if one wants the same rate as parent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (rate == parent_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) val = readl(asiu->div_base + clk->div.offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) val &= ~(1 << clk->div.en_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) writel(val, asiu->div_base + clk->div.offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) div = DIV_ROUND_CLOSEST(parent_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (div < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) div_h = div_l = div >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) div_h--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) div_l--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) val = readl(asiu->div_base + clk->div.offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) val |= 1 << clk->div.en_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (div_h) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) val &= ~(bit_mask(clk->div.high_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) << clk->div.high_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) val |= div_h << clk->div.high_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) val &= ~(bit_mask(clk->div.high_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) << clk->div.high_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (div_l) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) val |= div_l << clk->div.low_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) writel(val, asiu->div_base + clk->div.offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const struct clk_ops iproc_asiu_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .enable = iproc_asiu_clk_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .disable = iproc_asiu_clk_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .recalc_rate = iproc_asiu_clk_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .round_rate = iproc_asiu_clk_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .set_rate = iproc_asiu_clk_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) void __init iproc_asiu_setup(struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) const struct iproc_asiu_div *div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) const struct iproc_asiu_gate *gate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned int num_clks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct iproc_asiu *asiu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (WARN_ON(!gate || !div))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) asiu = kzalloc(sizeof(*asiu), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (WARN_ON(!asiu))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) asiu->clk_data = kzalloc(struct_size(asiu->clk_data, hws, num_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (WARN_ON(!asiu->clk_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) goto err_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) asiu->clk_data->num = num_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) asiu->clks = kcalloc(num_clks, sizeof(*asiu->clks), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (WARN_ON(!asiu->clks))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) goto err_asiu_clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) asiu->div_base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (WARN_ON(!asiu->div_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) goto err_iomap_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) asiu->gate_base = of_iomap(node, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (WARN_ON(!asiu->gate_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) goto err_iomap_gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) for (i = 0; i < num_clks; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct iproc_asiu_clk *asiu_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) const char *clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ret = of_property_read_string_index(node, "clock-output-names",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) i, &clk_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (WARN_ON(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) goto err_clk_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) asiu_clk = &asiu->clks[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) asiu_clk->name = clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) asiu_clk->asiu = asiu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) asiu_clk->div = div[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) asiu_clk->gate = gate[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) init.name = clk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) init.ops = &iproc_asiu_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) parent_name = of_clk_get_parent_name(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) init.parent_names = (parent_name ? &parent_name : NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) init.num_parents = (parent_name ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) asiu_clk->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ret = clk_hw_register(NULL, &asiu_clk->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (WARN_ON(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) goto err_clk_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) asiu->clk_data->hws[i] = &asiu_clk->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) asiu->clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (WARN_ON(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) goto err_clk_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) err_clk_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) while (--i >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) clk_hw_unregister(asiu->clk_data->hws[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) iounmap(asiu->gate_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) err_iomap_gate:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) iounmap(asiu->div_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) err_iomap_div:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) kfree(asiu->clks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) err_asiu_clks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) kfree(asiu->clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) err_clks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) kfree(asiu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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