^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2014 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "clk-iproc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IPROC_CLK_MAX_FREQ_POLICY 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IPROC_CLK_POLICY_FREQ_OFFSET 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IPROC_CLK_POLICY_FREQ_POLICY_FREQ_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IPROC_CLK_POLICY_FREQ_POLICY_FREQ_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IPROC_CLK_PLLARMA_OFFSET 0xc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IPROC_CLK_PLLARMA_LOCK_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IPROC_CLK_PLLARMA_PDIV_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IPROC_CLK_PLLARMA_PDIV_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IPROC_CLK_PLLARMA_NDIV_INT_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IPROC_CLK_PLLARMA_NDIV_INT_MASK 0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IPROC_CLK_PLLARMB_OFFSET 0xc04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IPROC_CLK_PLLARMB_NDIV_FRAC_MASK 0xfffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IPROC_CLK_PLLARMC_OFFSET 0xc08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IPROC_CLK_PLLARMC_BYPCLK_EN_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IPROC_CLK_PLLARMC_MDIV_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IPROC_CLK_PLLARMCTL5_OFFSET 0xc20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IPROC_CLK_PLLARMCTL5_H_MDIV_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IPROC_CLK_PLLARM_OFFSET_OFFSET 0xc24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IPROC_CLK_PLLARM_SW_CTL_SHIFT 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IPROC_CLK_PLLARM_NDIV_INT_OFFSET_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IPROC_CLK_PLLARM_NDIV_INT_OFFSET_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IPROC_CLK_PLLARM_NDIV_FRAC_OFFSET_MASK 0xfffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IPROC_CLK_ARM_DIV_OFFSET 0xe00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IPROC_CLK_ARM_DIV_PLL_SELECT_OVERRIDE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IPROC_CLK_ARM_DIV_ARM_PLL_SELECT_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IPROC_CLK_POLICY_DBG_OFFSET 0xec0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IPROC_CLK_POLICY_DBG_ACT_FREQ_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IPROC_CLK_POLICY_DBG_ACT_FREQ_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) enum iproc_arm_pll_fid {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ARM_PLL_FID_CRYSTAL_CLK = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ARM_PLL_FID_SYS_CLK = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ARM_PLL_FID_CH0_SLOW_CLK = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ARM_PLL_FID_CH1_FAST_CLK = 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct iproc_arm_pll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define to_iproc_arm_pll(hw) container_of(hw, struct iproc_arm_pll, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static unsigned int __get_fid(struct iproc_arm_pll *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned int policy, fid, active_fid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (val & (1 << IPROC_CLK_ARM_DIV_PLL_SELECT_OVERRIDE_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) policy = val & IPROC_CLK_ARM_DIV_ARM_PLL_SELECT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) policy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* something is seriously wrong */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) BUG_ON(policy > IPROC_CLK_MAX_FREQ_POLICY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) fid = (val >> (IPROC_CLK_POLICY_FREQ_POLICY_FREQ_SHIFT * policy)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) IPROC_CLK_POLICY_FREQ_POLICY_FREQ_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) active_fid = IPROC_CLK_POLICY_DBG_ACT_FREQ_MASK &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) (val >> IPROC_CLK_POLICY_DBG_ACT_FREQ_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (fid != active_fid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) pr_debug("%s: fid override %u->%u\n", __func__, fid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) active_fid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) fid = active_fid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) pr_debug("%s: active fid: %u\n", __func__, fid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return fid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * Determine the mdiv (post divider) based on the frequency ID being used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * There are 4 sources that can be used to derive the output clock rate:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * - 25 MHz Crystal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * - System clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * - PLL channel 0 (slow clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * - PLL channel 1 (fast clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int __get_mdiv(struct iproc_arm_pll *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned int fid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int mdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) fid = __get_fid(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) switch (fid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) case ARM_PLL_FID_CRYSTAL_CLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) case ARM_PLL_FID_SYS_CLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) mdiv = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) case ARM_PLL_FID_CH0_SLOW_CLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) mdiv = val & IPROC_CLK_PLLARMC_MDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (mdiv == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) mdiv = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) case ARM_PLL_FID_CH1_FAST_CLK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) val = readl(pll->base + IPROC_CLK_PLLARMCTL5_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) mdiv = val & IPROC_CLK_PLLARMCTL5_H_MDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (mdiv == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) mdiv = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) mdiv = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return mdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static unsigned int __get_ndiv(struct iproc_arm_pll *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned int ndiv_int, ndiv_frac, ndiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) val = readl(pll->base + IPROC_CLK_PLLARM_OFFSET_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (val & (1 << IPROC_CLK_PLLARM_SW_CTL_SHIFT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * offset mode is active. Read the ndiv from the PLLARM OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ndiv_int = (val >> IPROC_CLK_PLLARM_NDIV_INT_OFFSET_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) IPROC_CLK_PLLARM_NDIV_INT_OFFSET_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (ndiv_int == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ndiv_int = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ndiv_frac = val & IPROC_CLK_PLLARM_NDIV_FRAC_OFFSET_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* offset mode not active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) val = readl(pll->base + IPROC_CLK_PLLARMA_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ndiv_int = (val >> IPROC_CLK_PLLARMA_NDIV_INT_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) IPROC_CLK_PLLARMA_NDIV_INT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (ndiv_int == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) ndiv_int = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) val = readl(pll->base + IPROC_CLK_PLLARMB_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ndiv_frac = val & IPROC_CLK_PLLARMB_NDIV_FRAC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ndiv = (ndiv_int << 20) | ndiv_frac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return ndiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * The output frequency of the ARM PLL is calculated based on the ARM PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * divider values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * pdiv = ARM PLL pre-divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * ndiv = ARM PLL multiplier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * mdiv = ARM PLL post divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * The frequency is calculated by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * ((ndiv * parent clock rate) / pdiv) / mdiv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static unsigned long iproc_arm_pll_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct iproc_arm_pll *pll = to_iproc_arm_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int mdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u64 ndiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned int pdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* in bypass mode, use parent rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (val & (1 << IPROC_CLK_PLLARMC_BYPCLK_EN_SHIFT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) pll->rate = parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return pll->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* PLL needs to be locked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) val = readl(pll->base + IPROC_CLK_PLLARMA_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (!(val & (1 << IPROC_CLK_PLLARMA_LOCK_SHIFT))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) pll->rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) pdiv = (val >> IPROC_CLK_PLLARMA_PDIV_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) IPROC_CLK_PLLARMA_PDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (pdiv == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) pdiv = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ndiv = __get_ndiv(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) mdiv = __get_mdiv(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (mdiv <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) pll->rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) pll->rate = (ndiv * parent_rate) >> 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) pll->rate = (pll->rate / pdiv) / mdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) pr_debug("%s: ARM PLL rate: %lu. parent rate: %lu\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) pll->rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) pr_debug("%s: ndiv_int: %u, pdiv: %u, mdiv: %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) (unsigned int)(ndiv >> 20), pdiv, mdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return pll->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static const struct clk_ops iproc_arm_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .recalc_rate = iproc_arm_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) void __init iproc_armpll_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct iproc_arm_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) pll = kzalloc(sizeof(*pll), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (WARN_ON(!pll))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pll->base = of_iomap(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (WARN_ON(!pll->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) goto err_free_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) init.name = node->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) init.ops = &iproc_arm_pll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) parent_name = of_clk_get_parent_name(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) init.parent_names = (parent_name ? &parent_name : NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) init.num_parents = (parent_name ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) pll->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ret = clk_hw_register(NULL, &pll->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (WARN_ON(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) goto err_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (WARN_ON(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) goto err_clk_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) err_clk_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) clk_hw_unregister(&pll->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) err_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) iounmap(pll->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) err_free_pll:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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