^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2014 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <dt-bindings/clock/bcm-cygnus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "clk-iproc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .pwr_shift = ps, .iso_shift = is }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SW_CTRL_VAL(o, s) { .offset = o, .shift = s, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ASIU_DIV_VAL(o, es, hs, hw, ls, lw) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { .offset = o, .en_shift = es, .high_shift = hs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .high_width = hw, .low_shift = ls, .low_width = lw }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .p_reset_shift = prs }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .ka_width = kaw }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .hold_shift = hs, .bypass_shift = bs }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ASIU_GATE_VAL(o, es) { .offset = o, .en_shift = es }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static void __init cygnus_armpll_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) iproc_armpll_setup(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static const struct iproc_pll_ctrl genpll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) IPROC_CLK_PLL_NEEDS_SW_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .aon = AON_VAL(0x0, 2, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .reset = RESET_VAL(0x0, 11, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .sw_ctrl = SW_CTRL_VAL(0x10, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .ndiv_int = REG_VAL(0x10, 20, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .ndiv_frac = REG_VAL(0x10, 0, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .pdiv = REG_VAL(0x14, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .vco_ctrl = VCO_CTRL_VAL(0x18, 0x1c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .status = REG_VAL(0x28, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static const struct iproc_clk_ctrl genpll_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) [BCM_CYGNUS_GENPLL_AXI21_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .channel = BCM_CYGNUS_GENPLL_AXI21_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .enable = ENABLE_VAL(0x4, 6, 0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .mdiv = REG_VAL(0x20, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) [BCM_CYGNUS_GENPLL_250MHZ_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .channel = BCM_CYGNUS_GENPLL_250MHZ_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .enable = ENABLE_VAL(0x4, 7, 1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .mdiv = REG_VAL(0x20, 10, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) [BCM_CYGNUS_GENPLL_IHOST_SYS_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .enable = ENABLE_VAL(0x4, 8, 2, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .mdiv = REG_VAL(0x20, 20, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) [BCM_CYGNUS_GENPLL_ENET_SW_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .channel = BCM_CYGNUS_GENPLL_ENET_SW_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .enable = ENABLE_VAL(0x4, 9, 3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .mdiv = REG_VAL(0x24, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) [BCM_CYGNUS_GENPLL_AUDIO_125_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .channel = BCM_CYGNUS_GENPLL_AUDIO_125_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .enable = ENABLE_VAL(0x4, 10, 4, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .mdiv = REG_VAL(0x24, 10, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) [BCM_CYGNUS_GENPLL_CAN_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .channel = BCM_CYGNUS_GENPLL_CAN_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .enable = ENABLE_VAL(0x4, 11, 5, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .mdiv = REG_VAL(0x24, 20, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static void __init cygnus_genpll_clk_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) iproc_pll_clk_setup(node, &genpll, NULL, 0, genpll_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ARRAY_SIZE(genpll_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) CLK_OF_DECLARE(cygnus_genpll, "brcm,cygnus-genpll", cygnus_genpll_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static const struct iproc_pll_ctrl lcpll0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .aon = AON_VAL(0x0, 2, 5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .reset = RESET_VAL(0x0, 31, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .dig_filter = DF_VAL(0x0, 27, 3, 23, 4, 19, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .sw_ctrl = SW_CTRL_VAL(0x4, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .ndiv_int = REG_VAL(0x4, 16, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .pdiv = REG_VAL(0x4, 26, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .vco_ctrl = VCO_CTRL_VAL(0x10, 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .status = REG_VAL(0x18, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const struct iproc_clk_ctrl lcpll0_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) [BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .channel = BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .enable = ENABLE_VAL(0x0, 7, 1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .mdiv = REG_VAL(0x8, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) [BCM_CYGNUS_LCPLL0_DDR_PHY_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .channel = BCM_CYGNUS_LCPLL0_DDR_PHY_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .enable = ENABLE_VAL(0x0, 8, 2, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .mdiv = REG_VAL(0x8, 10, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) [BCM_CYGNUS_LCPLL0_SDIO_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .channel = BCM_CYGNUS_LCPLL0_SDIO_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .enable = ENABLE_VAL(0x0, 9, 3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .mdiv = REG_VAL(0x8, 20, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) [BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .channel = BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .enable = ENABLE_VAL(0x0, 10, 4, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .mdiv = REG_VAL(0xc, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) [BCM_CYGNUS_LCPLL0_SMART_CARD_CLK] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .channel = BCM_CYGNUS_LCPLL0_SMART_CARD_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .enable = ENABLE_VAL(0x0, 11, 5, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .mdiv = REG_VAL(0xc, 10, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) [BCM_CYGNUS_LCPLL0_CH5_UNUSED] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .channel = BCM_CYGNUS_LCPLL0_CH5_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .enable = ENABLE_VAL(0x0, 12, 6, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .mdiv = REG_VAL(0xc, 20, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static void __init cygnus_lcpll0_clk_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) iproc_pll_clk_setup(node, &lcpll0, NULL, 0, lcpll0_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ARRAY_SIZE(lcpll0_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) CLK_OF_DECLARE(cygnus_lcpll0, "brcm,cygnus-lcpll0", cygnus_lcpll0_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * MIPI PLL VCO frequency parameter table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const struct iproc_pll_vco_param mipipll_vco_params[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* rate (Hz) ndiv_int ndiv_frac pdiv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { 750000000UL, 30, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { 1000000000UL, 40, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { 1350000000ul, 54, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { 2000000000UL, 80, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { 2100000000UL, 84, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { 2250000000UL, 90, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { 2500000000UL, 100, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { 2700000000UL, 54, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { 2975000000UL, 119, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { 3100000000UL, 124, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { 3150000000UL, 126, 0, 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static const struct iproc_pll_ctrl mipipll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .flags = IPROC_CLK_PLL_ASIU | IPROC_CLK_PLL_HAS_NDIV_FRAC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) IPROC_CLK_NEEDS_READ_BACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .aon = AON_VAL(0x0, 4, 17, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .asiu = ASIU_GATE_VAL(0x0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .reset = RESET_VAL(0x0, 11, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .ndiv_int = REG_VAL(0x10, 20, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .ndiv_frac = REG_VAL(0x10, 0, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .pdiv = REG_VAL(0x14, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .vco_ctrl = VCO_CTRL_VAL(0x18, 0x1c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .status = REG_VAL(0x28, 12, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const struct iproc_clk_ctrl mipipll_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) [BCM_CYGNUS_MIPIPLL_CH0_UNUSED] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .channel = BCM_CYGNUS_MIPIPLL_CH0_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .flags = IPROC_CLK_NEEDS_READ_BACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .enable = ENABLE_VAL(0x4, 12, 6, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .mdiv = REG_VAL(0x20, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) [BCM_CYGNUS_MIPIPLL_CH1_LCD] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .channel = BCM_CYGNUS_MIPIPLL_CH1_LCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .flags = IPROC_CLK_NEEDS_READ_BACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .enable = ENABLE_VAL(0x4, 13, 7, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .mdiv = REG_VAL(0x20, 10, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) [BCM_CYGNUS_MIPIPLL_CH2_V3D] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .channel = BCM_CYGNUS_MIPIPLL_CH2_V3D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .flags = IPROC_CLK_NEEDS_READ_BACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .enable = ENABLE_VAL(0x4, 14, 8, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .mdiv = REG_VAL(0x20, 20, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) [BCM_CYGNUS_MIPIPLL_CH3_UNUSED] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .channel = BCM_CYGNUS_MIPIPLL_CH3_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .flags = IPROC_CLK_NEEDS_READ_BACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .enable = ENABLE_VAL(0x4, 15, 9, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .mdiv = REG_VAL(0x24, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) [BCM_CYGNUS_MIPIPLL_CH4_UNUSED] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .channel = BCM_CYGNUS_MIPIPLL_CH4_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .flags = IPROC_CLK_NEEDS_READ_BACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .enable = ENABLE_VAL(0x4, 16, 10, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .mdiv = REG_VAL(0x24, 10, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) [BCM_CYGNUS_MIPIPLL_CH5_UNUSED] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .channel = BCM_CYGNUS_MIPIPLL_CH5_UNUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .flags = IPROC_CLK_NEEDS_READ_BACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .enable = ENABLE_VAL(0x4, 17, 11, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .mdiv = REG_VAL(0x24, 20, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static void __init cygnus_mipipll_clk_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) iproc_pll_clk_setup(node, &mipipll, mipipll_vco_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ARRAY_SIZE(mipipll_vco_params), mipipll_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ARRAY_SIZE(mipipll_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) CLK_OF_DECLARE(cygnus_mipipll, "brcm,cygnus-mipipll", cygnus_mipipll_clk_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static const struct iproc_asiu_div asiu_div[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) [BCM_CYGNUS_ASIU_KEYPAD_CLK] = ASIU_DIV_VAL(0x0, 31, 16, 10, 0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) [BCM_CYGNUS_ASIU_ADC_CLK] = ASIU_DIV_VAL(0x4, 31, 16, 10, 0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) [BCM_CYGNUS_ASIU_PWM_CLK] = ASIU_DIV_VAL(0x8, 31, 16, 10, 0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const struct iproc_asiu_gate asiu_gate[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) [BCM_CYGNUS_ASIU_KEYPAD_CLK] = ASIU_GATE_VAL(0x0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) [BCM_CYGNUS_ASIU_ADC_CLK] = ASIU_GATE_VAL(0x0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) [BCM_CYGNUS_ASIU_PWM_CLK] = ASIU_GATE_VAL(IPROC_CLK_INVALID_OFFSET, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static void __init cygnus_asiu_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) iproc_asiu_setup(node, asiu_div, asiu_gate, ARRAY_SIZE(asiu_div));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) CLK_OF_DECLARE(cygnus_asiu_clk, "brcm,cygnus-asiu-clk", cygnus_asiu_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const struct iproc_pll_ctrl audiopll = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .flags = IPROC_CLK_PLL_NEEDS_SW_CFG | IPROC_CLK_PLL_HAS_NDIV_FRAC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) IPROC_CLK_PLL_USER_MODE_ON | IPROC_CLK_PLL_RESET_ACTIVE_LOW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) IPROC_CLK_PLL_CALC_PARAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .reset = RESET_VAL(0x5c, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .dig_filter = DF_VAL(0x48, 0, 3, 6, 4, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .sw_ctrl = SW_CTRL_VAL(0x4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .ndiv_int = REG_VAL(0x8, 0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .ndiv_frac = REG_VAL(0x8, 10, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .pdiv = REG_VAL(0x44, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .vco_ctrl = VCO_CTRL_VAL(0x0c, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .status = REG_VAL(0x54, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .macro_mode = REG_VAL(0x0, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static const struct iproc_clk_ctrl audiopll_clk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) [BCM_CYGNUS_AUDIOPLL_CH0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .channel = BCM_CYGNUS_AUDIOPLL_CH0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .flags = IPROC_CLK_AON | IPROC_CLK_MCLK_DIV_BY_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .enable = ENABLE_VAL(0x14, 8, 10, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .mdiv = REG_VAL(0x14, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) [BCM_CYGNUS_AUDIOPLL_CH1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .channel = BCM_CYGNUS_AUDIOPLL_CH1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .enable = ENABLE_VAL(0x18, 8, 10, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .mdiv = REG_VAL(0x18, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) [BCM_CYGNUS_AUDIOPLL_CH2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .channel = BCM_CYGNUS_AUDIOPLL_CH2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .flags = IPROC_CLK_AON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .enable = ENABLE_VAL(0x1c, 8, 10, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .mdiv = REG_VAL(0x1c, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static void __init cygnus_audiopll_clk_init(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) iproc_pll_clk_setup(node, &audiopll, NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) audiopll_clk, ARRAY_SIZE(audiopll_clk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) CLK_OF_DECLARE(cygnus_audiopll, "brcm,cygnus-audiopll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) cygnus_audiopll_clk_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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