^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <dt-bindings/clock/bcm3368-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <dt-bindings/clock/bcm6318-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <dt-bindings/clock/bcm6328-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <dt-bindings/clock/bcm6358-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <dt-bindings/clock/bcm6362-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <dt-bindings/clock/bcm6368-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <dt-bindings/clock/bcm63268-clock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct clk_bcm63xx_table_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) const char * const name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u8 bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct clk_bcm63xx_hw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct clk_hw_onecell_data data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static const struct clk_bcm63xx_table_entry bcm3368_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .name = "mac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .bit = BCM3368_CLK_MAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .name = "tc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .bit = BCM3368_CLK_TC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .name = "us_top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .bit = BCM3368_CLK_US_TOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .name = "ds_top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .bit = BCM3368_CLK_DS_TOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .name = "acm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .bit = BCM3368_CLK_ACM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .name = "spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .bit = BCM3368_CLK_SPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .name = "usbs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .bit = BCM3368_CLK_USBS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .name = "bmu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .bit = BCM3368_CLK_BMU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .name = "pcm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .bit = BCM3368_CLK_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .name = "ntp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .bit = BCM3368_CLK_NTP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .name = "acp_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .bit = BCM3368_CLK_ACP_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .name = "acp_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .bit = BCM3368_CLK_ACP_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .name = "emusb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .bit = BCM3368_CLK_EMUSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .name = "enet0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .bit = BCM3368_CLK_ENET0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .name = "enet1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .bit = BCM3368_CLK_ENET1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .name = "usbsu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .bit = BCM3368_CLK_USBSU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .name = "ephy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .bit = BCM3368_CLK_EPHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static const struct clk_bcm63xx_table_entry bcm6318_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .name = "adsl_asb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .bit = BCM6318_CLK_ADSL_ASB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .name = "usb_asb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .bit = BCM6318_CLK_USB_ASB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .name = "mips_asb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .bit = BCM6318_CLK_MIPS_ASB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .name = "pcie_asb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .bit = BCM6318_CLK_PCIE_ASB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .name = "phymips_asb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .bit = BCM6318_CLK_PHYMIPS_ASB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .name = "robosw_asb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .bit = BCM6318_CLK_ROBOSW_ASB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .name = "sar_asb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .bit = BCM6318_CLK_SAR_ASB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .name = "sdr_asb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .bit = BCM6318_CLK_SDR_ASB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .name = "swreg_asb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .bit = BCM6318_CLK_SWREG_ASB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .name = "periph_asb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .bit = BCM6318_CLK_PERIPH_ASB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .name = "cpubus160",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .bit = BCM6318_CLK_CPUBUS160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .name = "adsl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .bit = BCM6318_CLK_ADSL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .name = "sar125",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .bit = BCM6318_CLK_SAR125,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .name = "mips",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .bit = BCM6318_CLK_MIPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .name = "pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .bit = BCM6318_CLK_PCIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .name = "robosw250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .bit = BCM6318_CLK_ROBOSW250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .name = "robosw025",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .bit = BCM6318_CLK_ROBOSW025,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .name = "sdr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .bit = BCM6318_CLK_SDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .name = "usbd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .bit = BCM6318_CLK_USBD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .name = "hsspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .bit = BCM6318_CLK_HSSPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .name = "pcie25",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .bit = BCM6318_CLK_PCIE25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .name = "phymips",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .bit = BCM6318_CLK_PHYMIPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .name = "afe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .bit = BCM6318_CLK_AFE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .name = "qproc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .bit = BCM6318_CLK_QPROC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const struct clk_bcm63xx_table_entry bcm6318_ubus_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .name = "adsl-ubus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .bit = BCM6318_UCLK_ADSL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .name = "arb-ubus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .bit = BCM6318_UCLK_ARB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .name = "mips-ubus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .bit = BCM6318_UCLK_MIPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .name = "pcie-ubus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .bit = BCM6318_UCLK_PCIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .name = "periph-ubus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .bit = BCM6318_UCLK_PERIPH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .name = "phymips-ubus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .bit = BCM6318_UCLK_PHYMIPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .name = "robosw-ubus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .bit = BCM6318_UCLK_ROBOSW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .name = "sar-ubus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .bit = BCM6318_UCLK_SAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .name = "sdr-ubus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .bit = BCM6318_UCLK_SDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .name = "usb-ubus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .bit = BCM6318_UCLK_USB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static const struct clk_bcm63xx_table_entry bcm6328_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .name = "phy_mips",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .bit = BCM6328_CLK_PHYMIPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .name = "adsl_qproc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .bit = BCM6328_CLK_ADSL_QPROC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .name = "adsl_afe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .bit = BCM6328_CLK_ADSL_AFE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .name = "adsl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .bit = BCM6328_CLK_ADSL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .name = "mips",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .bit = BCM6328_CLK_MIPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .name = "sar",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .bit = BCM6328_CLK_SAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .name = "pcm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .bit = BCM6328_CLK_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .name = "usbd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .bit = BCM6328_CLK_USBD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .name = "usbh",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .bit = BCM6328_CLK_USBH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .name = "hsspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .bit = BCM6328_CLK_HSSPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .name = "pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .bit = BCM6328_CLK_PCIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .name = "robosw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .bit = BCM6328_CLK_ROBOSW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static const struct clk_bcm63xx_table_entry bcm6358_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .name = "enet",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .bit = BCM6358_CLK_ENET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .name = "adslphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .bit = BCM6358_CLK_ADSLPHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .name = "pcm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .bit = BCM6358_CLK_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .name = "spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .bit = BCM6358_CLK_SPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .name = "usbs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .bit = BCM6358_CLK_USBS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .name = "sar",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .bit = BCM6358_CLK_SAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .name = "emusb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .bit = BCM6358_CLK_EMUSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .name = "enet0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .bit = BCM6358_CLK_ENET0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .name = "enet1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .bit = BCM6358_CLK_ENET1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .name = "usbsu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .bit = BCM6358_CLK_USBSU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .name = "ephy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .bit = BCM6358_CLK_EPHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static const struct clk_bcm63xx_table_entry bcm6362_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .name = "adsl_qproc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .bit = BCM6362_CLK_ADSL_QPROC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .name = "adsl_afe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .bit = BCM6362_CLK_ADSL_AFE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .name = "adsl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .bit = BCM6362_CLK_ADSL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .name = "mips",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .bit = BCM6362_CLK_MIPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .name = "wlan_ocp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .bit = BCM6362_CLK_WLAN_OCP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .name = "swpkt_usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .bit = BCM6362_CLK_SWPKT_USB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .name = "swpkt_sar",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .bit = BCM6362_CLK_SWPKT_SAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .name = "sar",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .bit = BCM6362_CLK_SAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .name = "robosw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .bit = BCM6362_CLK_ROBOSW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .name = "pcm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .bit = BCM6362_CLK_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .name = "usbd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .bit = BCM6362_CLK_USBD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .name = "usbh",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .bit = BCM6362_CLK_USBH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .name = "ipsec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .bit = BCM6362_CLK_IPSEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .name = "spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .bit = BCM6362_CLK_SPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .name = "hsspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .bit = BCM6362_CLK_HSSPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .name = "pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .bit = BCM6362_CLK_PCIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .name = "fap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .bit = BCM6362_CLK_FAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .name = "phymips",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .bit = BCM6362_CLK_PHYMIPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .name = "nand",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .bit = BCM6362_CLK_NAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static const struct clk_bcm63xx_table_entry bcm6368_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .name = "vdsl_qproc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .bit = BCM6368_CLK_VDSL_QPROC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .name = "vdsl_afe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .bit = BCM6368_CLK_VDSL_AFE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .name = "vdsl_bonding",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .bit = BCM6368_CLK_VDSL_BONDING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .name = "vdsl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .bit = BCM6368_CLK_VDSL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .name = "phymips",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .bit = BCM6368_CLK_PHYMIPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .name = "swpkt_usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .bit = BCM6368_CLK_SWPKT_USB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .name = "swpkt_sar",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .bit = BCM6368_CLK_SWPKT_SAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .name = "spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .bit = BCM6368_CLK_SPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .name = "usbd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .bit = BCM6368_CLK_USBD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .name = "sar",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .bit = BCM6368_CLK_SAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .name = "robosw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .bit = BCM6368_CLK_ROBOSW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .name = "utopia",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .bit = BCM6368_CLK_UTOPIA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .name = "pcm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .bit = BCM6368_CLK_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .name = "usbh",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .bit = BCM6368_CLK_USBH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .name = "disable_gless",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .bit = BCM6368_CLK_DIS_GLESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .name = "nand",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .bit = BCM6368_CLK_NAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .name = "ipsec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .bit = BCM6368_CLK_IPSEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static const struct clk_bcm63xx_table_entry bcm63268_clocks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .name = "disable_gless",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .bit = BCM63268_CLK_DIS_GLESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .name = "vdsl_qproc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .bit = BCM63268_CLK_VDSL_QPROC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .name = "vdsl_afe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .bit = BCM63268_CLK_VDSL_AFE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .name = "vdsl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .bit = BCM63268_CLK_VDSL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .name = "mips",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .bit = BCM63268_CLK_MIPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .name = "wlan_ocp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .bit = BCM63268_CLK_WLAN_OCP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .name = "dect",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .bit = BCM63268_CLK_DECT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .name = "fap0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .bit = BCM63268_CLK_FAP0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .name = "fap1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .bit = BCM63268_CLK_FAP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .name = "sar",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .bit = BCM63268_CLK_SAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .name = "robosw",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .bit = BCM63268_CLK_ROBOSW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .name = "pcm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .bit = BCM63268_CLK_PCM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .name = "usbd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .bit = BCM63268_CLK_USBD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .name = "usbh",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .bit = BCM63268_CLK_USBH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .name = "ipsec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .bit = BCM63268_CLK_IPSEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .name = "spi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .bit = BCM63268_CLK_SPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .name = "hsspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .bit = BCM63268_CLK_HSSPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .name = "pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .bit = BCM63268_CLK_PCIE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .name = "phymips",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .bit = BCM63268_CLK_PHYMIPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .name = "gmac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .bit = BCM63268_CLK_GMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .name = "nand",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .bit = BCM63268_CLK_NAND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .name = "tbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .bit = BCM63268_CLK_TBUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .name = "robosw250",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .bit = BCM63268_CLK_ROBOSW250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int clk_bcm63xx_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) const struct clk_bcm63xx_table_entry *entry, *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct clk_bcm63xx_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) u8 maxbit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) table = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (!table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) for (entry = table; entry->name; entry++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) maxbit = max_t(u8, maxbit, entry->bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) maxbit++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) hw = devm_kzalloc(&pdev->dev, struct_size(hw, data.hws, maxbit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (!hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) platform_set_drvdata(pdev, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) spin_lock_init(&hw->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) hw->data.num = maxbit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) for (i = 0; i < maxbit; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) hw->data.hws[i] = ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) hw->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (IS_ERR(hw->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return PTR_ERR(hw->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) for (entry = table; entry->name; entry++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct clk_hw *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) clk = clk_hw_register_gate(&pdev->dev, entry->name, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) entry->flags, hw->regs, entry->bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) CLK_GATE_BIG_ENDIAN, &hw->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (IS_ERR(clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ret = PTR_ERR(clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) hw->data.hws[entry->bit] = clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) &hw->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) for (i = 0; i < hw->data.num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (!IS_ERR(hw->data.hws[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) clk_hw_unregister_gate(hw->data.hws[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static int clk_bcm63xx_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct clk_bcm63xx_hw *hw = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) of_clk_del_provider(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) for (i = 0; i < hw->data.num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (!IS_ERR(hw->data.hws[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) clk_hw_unregister_gate(hw->data.hws[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static const struct of_device_id clk_bcm63xx_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) { .compatible = "brcm,bcm3368-clocks", .data = &bcm3368_clocks, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) { .compatible = "brcm,bcm6318-clocks", .data = &bcm6318_clocks, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) { .compatible = "brcm,bcm6318-ubus-clocks", .data = &bcm6318_ubus_clocks, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) { .compatible = "brcm,bcm6328-clocks", .data = &bcm6328_clocks, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) { .compatible = "brcm,bcm6358-clocks", .data = &bcm6358_clocks, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) { .compatible = "brcm,bcm6362-clocks", .data = &bcm6362_clocks, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) { .compatible = "brcm,bcm6368-clocks", .data = &bcm6368_clocks, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) { .compatible = "brcm,bcm63268-clocks", .data = &bcm63268_clocks, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static struct platform_driver clk_bcm63xx = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .probe = clk_bcm63xx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .remove = clk_bcm63xx_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .name = "bcm63xx-clock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .of_match_table = clk_bcm63xx_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) builtin_platform_driver(clk_bcm63xx);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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