^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PMU_XTAL_FREQ_RATIO 0x66c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define XTAL_ALP_PER_4ILP 0x00001fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define XTAL_CTL_EN 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PMU_SLOW_CLK_PERIOD 0x6dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct bcm53573_ilp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static int bcm53573_ilp_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct bcm53573_ilp *ilp = container_of(hw, struct bcm53573_ilp, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) regmap_write(ilp->regmap, PMU_SLOW_CLK_PERIOD, 0x10199);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) regmap_write(ilp->regmap, 0x674, 0x10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static void bcm53573_ilp_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct bcm53573_ilp *ilp = container_of(hw, struct bcm53573_ilp, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) regmap_write(ilp->regmap, PMU_SLOW_CLK_PERIOD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) regmap_write(ilp->regmap, 0x674, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static unsigned long bcm53573_ilp_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct bcm53573_ilp *ilp = container_of(hw, struct bcm53573_ilp, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct regmap *regmap = ilp->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 last_val, cur_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int sum = 0, num = 0, loop_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int avg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Enable measurement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) regmap_write(regmap, PMU_XTAL_FREQ_RATIO, XTAL_CTL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Read initial value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) regmap_read(regmap, PMU_XTAL_FREQ_RATIO, &last_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) last_val &= XTAL_ALP_PER_4ILP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * At minimum we should loop for a bit to let hardware do the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * measurement. This isn't very accurate however, so for a better
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * precision lets try getting 20 different values for and use average.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) while (num < 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) regmap_read(regmap, PMU_XTAL_FREQ_RATIO, &cur_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) cur_val &= XTAL_ALP_PER_4ILP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (cur_val != last_val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Got different value, use it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) sum += cur_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) loop_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) last_val = cur_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) } else if (++loop_num > 5000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Same value over and over, give up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) sum += cur_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Disable measurement to save power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) regmap_write(regmap, PMU_XTAL_FREQ_RATIO, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) avg = sum / num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return parent_rate * 4 / avg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static const struct clk_ops bcm53573_ilp_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .enable = bcm53573_ilp_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .disable = bcm53573_ilp_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .recalc_rate = bcm53573_ilp_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static void bcm53573_ilp_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct bcm53573_ilp *ilp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct clk_init_data init = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ilp = kzalloc(sizeof(*ilp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (!ilp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) parent_name = of_clk_get_parent_name(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (!parent_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) err = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) goto err_free_ilp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ilp->regmap = syscon_node_to_regmap(of_get_parent(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (IS_ERR(ilp->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) err = PTR_ERR(ilp->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) goto err_free_ilp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) init.name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) init.ops = &bcm53573_ilp_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ilp->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) err = clk_hw_register(NULL, &ilp->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) goto err_free_ilp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) err = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &ilp->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) goto err_clk_hw_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) err_clk_hw_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) clk_hw_unregister(&ilp->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) err_free_ilp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) kfree(ilp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pr_err("Failed to init ILP clock: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* We need it very early for arch code, before device model gets ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) CLK_OF_DECLARE(bcm53573_ilp_clk, "brcm,bcm53573-ilp", bcm53573_ilp_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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