^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2010,2015 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 Stephen Warren
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * DOC: BCM2835 CPRMAN (clock manager for the "audio" domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * The clock tree on the 2835 has several levels. There's a root
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * oscillator running at 19.2Mhz. After the oscillator there are 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * PLLs, roughly divided as "camera", "ARM", "core", "DSI displays",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * and "HDMI displays". Those 5 PLLs each can divide their output to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * produce up to 4 channels. Finally, there is the level of clocks to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * be consumed by other hardware components (like "H264" or "HDMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * state machine"), which divide off of some subset of the PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * All of the clocks in the tree are exposed in the DT, because the DT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * may want to make assignments of the final layer of clocks to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * PLL channels, and some components of the hardware will actually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * skip layers of the tree (for example, the pixel clock comes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * directly from the PLLH PIX channel without using a CM_*CTL clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * generator).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <dt-bindings/clock/bcm2835.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CM_PASSWORD 0x5a000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CM_GNRICCTL 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CM_GNRICDIV 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) # define CM_DIV_FRAC_BITS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CM_VPUCTL 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CM_VPUDIV 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CM_SYSCTL 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CM_SYSDIV 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CM_PERIACTL 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CM_PERIADIV 0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CM_PERIICTL 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CM_PERIIDIV 0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CM_H264CTL 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CM_H264DIV 0x02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CM_ISPCTL 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CM_ISPDIV 0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CM_V3DCTL 0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CM_V3DDIV 0x03c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CM_CAM0CTL 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CM_CAM0DIV 0x044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CM_CAM1CTL 0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CM_CAM1DIV 0x04c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CM_CCP2CTL 0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CM_CCP2DIV 0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CM_DSI0ECTL 0x058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CM_DSI0EDIV 0x05c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CM_DSI0PCTL 0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CM_DSI0PDIV 0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CM_DPICTL 0x068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CM_DPIDIV 0x06c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CM_GP0CTL 0x070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CM_GP0DIV 0x074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CM_GP1CTL 0x078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CM_GP1DIV 0x07c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CM_GP2CTL 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CM_GP2DIV 0x084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CM_HSMCTL 0x088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CM_HSMDIV 0x08c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CM_OTPCTL 0x090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CM_OTPDIV 0x094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CM_PCMCTL 0x098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CM_PCMDIV 0x09c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CM_PWMCTL 0x0a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CM_PWMDIV 0x0a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CM_SLIMCTL 0x0a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CM_SLIMDIV 0x0ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CM_SMICTL 0x0b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CM_SMIDIV 0x0b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* no definition for 0x0b8 and 0x0bc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CM_TCNTCTL 0x0c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) # define CM_TCNT_SRC1_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CM_TCNTCNT 0x0c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CM_TECCTL 0x0c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CM_TECDIV 0x0cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CM_TD0CTL 0x0d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CM_TD0DIV 0x0d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CM_TD1CTL 0x0d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CM_TD1DIV 0x0dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CM_TSENSCTL 0x0e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CM_TSENSDIV 0x0e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CM_TIMERCTL 0x0e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CM_TIMERDIV 0x0ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CM_UARTCTL 0x0f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CM_UARTDIV 0x0f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CM_VECCTL 0x0f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CM_VECDIV 0x0fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CM_PULSECTL 0x190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CM_PULSEDIV 0x194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CM_SDCCTL 0x1a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CM_SDCDIV 0x1ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CM_ARMCTL 0x1b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CM_AVEOCTL 0x1b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CM_AVEODIV 0x1bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CM_EMMCCTL 0x1c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CM_EMMCDIV 0x1c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CM_EMMC2CTL 0x1d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CM_EMMC2DIV 0x1d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* General bits for the CM_*CTL regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) # define CM_ENABLE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) # define CM_KILL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) # define CM_GATE_BIT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) # define CM_GATE BIT(CM_GATE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) # define CM_BUSY BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) # define CM_BUSYD BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) # define CM_FRAC BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) # define CM_SRC_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) # define CM_SRC_BITS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) # define CM_SRC_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) # define CM_SRC_GND 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) # define CM_SRC_OSC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) # define CM_SRC_TESTDEBUG0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) # define CM_SRC_TESTDEBUG1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) # define CM_SRC_PLLA_CORE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) # define CM_SRC_PLLA_PER 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) # define CM_SRC_PLLC_CORE0 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) # define CM_SRC_PLLC_PER 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) # define CM_SRC_PLLC_CORE1 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) # define CM_SRC_PLLD_CORE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) # define CM_SRC_PLLD_PER 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) # define CM_SRC_PLLH_AUX 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) # define CM_SRC_PLLC_CORE1 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) # define CM_SRC_PLLC_CORE2 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CM_OSCCOUNT 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CM_PLLA 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) # define CM_PLL_ANARST BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) # define CM_PLLA_HOLDPER BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) # define CM_PLLA_LOADPER BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) # define CM_PLLA_HOLDCORE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) # define CM_PLLA_LOADCORE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) # define CM_PLLA_HOLDCCP2 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) # define CM_PLLA_LOADCCP2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) # define CM_PLLA_HOLDDSI0 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) # define CM_PLLA_LOADDSI0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CM_PLLC 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) # define CM_PLLC_HOLDPER BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) # define CM_PLLC_LOADPER BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) # define CM_PLLC_HOLDCORE2 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) # define CM_PLLC_LOADCORE2 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) # define CM_PLLC_HOLDCORE1 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) # define CM_PLLC_LOADCORE1 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) # define CM_PLLC_HOLDCORE0 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) # define CM_PLLC_LOADCORE0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CM_PLLD 0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) # define CM_PLLD_HOLDPER BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) # define CM_PLLD_LOADPER BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) # define CM_PLLD_HOLDCORE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) # define CM_PLLD_LOADCORE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) # define CM_PLLD_HOLDDSI1 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) # define CM_PLLD_LOADDSI1 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) # define CM_PLLD_HOLDDSI0 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) # define CM_PLLD_LOADDSI0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CM_PLLH 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) # define CM_PLLH_LOADRCAL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) # define CM_PLLH_LOADAUX BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) # define CM_PLLH_LOADPIX BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CM_LOCK 0x114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) # define CM_LOCK_FLOCKH BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) # define CM_LOCK_FLOCKD BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) # define CM_LOCK_FLOCKC BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) # define CM_LOCK_FLOCKB BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) # define CM_LOCK_FLOCKA BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CM_EVENT 0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CM_DSI1ECTL 0x158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CM_DSI1EDIV 0x15c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CM_DSI1PCTL 0x160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CM_DSI1PDIV 0x164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CM_DFTCTL 0x168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CM_DFTDIV 0x16c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CM_PLLB 0x170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) # define CM_PLLB_HOLDARM BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) # define CM_PLLB_LOADARM BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define A2W_PLLA_CTRL 0x1100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define A2W_PLLC_CTRL 0x1120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define A2W_PLLD_CTRL 0x1140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define A2W_PLLH_CTRL 0x1160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define A2W_PLLB_CTRL 0x11e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) # define A2W_PLL_CTRL_PRST_DISABLE BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) # define A2W_PLL_CTRL_PWRDN BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) # define A2W_PLL_CTRL_PDIV_MASK 0x000007000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) # define A2W_PLL_CTRL_PDIV_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) # define A2W_PLL_CTRL_NDIV_MASK 0x0000003ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) # define A2W_PLL_CTRL_NDIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define A2W_PLLA_ANA0 0x1010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define A2W_PLLC_ANA0 0x1030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define A2W_PLLD_ANA0 0x1050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define A2W_PLLH_ANA0 0x1070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define A2W_PLLB_ANA0 0x10f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define A2W_PLL_KA_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define A2W_PLL_KA_MASK GENMASK(9, 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define A2W_PLL_KI_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define A2W_PLL_KI_MASK GENMASK(21, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define A2W_PLL_KP_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define A2W_PLL_KP_MASK GENMASK(18, 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define A2W_PLLH_KA_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define A2W_PLLH_KA_MASK GENMASK(21, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define A2W_PLLH_KI_LOW_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define A2W_PLLH_KI_LOW_MASK GENMASK(23, 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define A2W_PLLH_KI_HIGH_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define A2W_PLLH_KI_HIGH_MASK GENMASK(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define A2W_PLLH_KP_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define A2W_PLLH_KP_MASK GENMASK(4, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define A2W_XOSC_CTRL 0x1190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) # define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) # define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) # define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) # define A2W_XOSC_CTRL_DDR_ENABLE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) # define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) # define A2W_XOSC_CTRL_USB_ENABLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) # define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) # define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define A2W_PLLA_FRAC 0x1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define A2W_PLLC_FRAC 0x1220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define A2W_PLLD_FRAC 0x1240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define A2W_PLLH_FRAC 0x1260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define A2W_PLLB_FRAC 0x12e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) # define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) # define A2W_PLL_FRAC_BITS 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define A2W_PLL_CHANNEL_DISABLE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define A2W_PLL_DIV_BITS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define A2W_PLL_DIV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define A2W_PLLA_DSI0 0x1300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define A2W_PLLA_CORE 0x1400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define A2W_PLLA_PER 0x1500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define A2W_PLLA_CCP2 0x1600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define A2W_PLLC_CORE2 0x1320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define A2W_PLLC_CORE1 0x1420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define A2W_PLLC_PER 0x1520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define A2W_PLLC_CORE0 0x1620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define A2W_PLLD_DSI0 0x1340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define A2W_PLLD_CORE 0x1440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define A2W_PLLD_PER 0x1540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define A2W_PLLD_DSI1 0x1640
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define A2W_PLLH_AUX 0x1360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define A2W_PLLH_RCAL 0x1460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define A2W_PLLH_PIX 0x1560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define A2W_PLLH_STS 0x1660
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define A2W_PLLH_CTRLR 0x1960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define A2W_PLLH_FRACR 0x1a60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define A2W_PLLH_AUXR 0x1b60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define A2W_PLLH_RCALR 0x1c60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define A2W_PLLH_PIXR 0x1d60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define A2W_PLLH_STSR 0x1e60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define A2W_PLLB_ARM 0x13e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define A2W_PLLB_SP0 0x14e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define A2W_PLLB_SP1 0x15e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define A2W_PLLB_SP2 0x16e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define LOCK_TIMEOUT_NS 100000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define BCM2835_MAX_FB_RATE 1750000000u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define SOC_BCM2835 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define SOC_BCM2711 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define SOC_ALL (SOC_BCM2835 | SOC_BCM2711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * Names of clocks used within the driver that need to be replaced
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * with an external parent's name. This array is in the order that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * the clocks node in the DT references external clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static const char *const cprman_parent_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) "xosc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) "dsi0_byte",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) "dsi0_ddr2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) "dsi0_ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) "dsi1_byte",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) "dsi1_ddr2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) "dsi1_ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct bcm2835_cprman {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) spinlock_t regs_lock; /* spinlock for all clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned int soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * Real names of cprman clock parents looked up through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * of_clk_get_parent_name(), which will be used in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * parent_names[] arrays for clock registration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) const char *real_parent_names[ARRAY_SIZE(cprman_parent_names)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* Must be last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct clk_hw_onecell_data onecell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct cprman_plat_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned int soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) writel(CM_PASSWORD | val, cprman->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static inline u32 cprman_read(struct bcm2835_cprman *cprman, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return readl(cprman->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Does a cycle of measuring a clock through the TCNT clock, which may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * source from many other clocks in the system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static unsigned long bcm2835_measure_tcnt_mux(struct bcm2835_cprman *cprman,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u32 tcnt_mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u32 osccount = 19200; /* 1ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) ktime_t timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) spin_lock(&cprman->regs_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) cprman_write(cprman, CM_TCNTCTL, CM_KILL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) cprman_write(cprman, CM_TCNTCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) (tcnt_mux & CM_SRC_MASK) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) (tcnt_mux >> CM_SRC_BITS) << CM_TCNT_SRC1_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) cprman_write(cprman, CM_OSCCOUNT, osccount);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* do a kind delay at the start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* Finish off whatever is left of OSCCOUNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) while (cprman_read(cprman, CM_OSCCOUNT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (ktime_after(ktime_get(), timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) dev_err(cprman->dev, "timeout waiting for OSCCOUNT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* Wait for BUSY to clear. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) while (cprman_read(cprman, CM_TCNTCTL) & CM_BUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (ktime_after(ktime_get(), timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dev_err(cprman->dev, "timeout waiting for !BUSY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) count = cprman_read(cprman, CM_TCNTCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) cprman_write(cprman, CM_TCNTCTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) spin_unlock(&cprman->regs_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return count * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static void bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) const struct debugfs_reg32 *regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) size_t nregs, struct dentry *dentry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct debugfs_regset32 *regset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (!regset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) regset->regs = regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) regset->nregs = nregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) regset->base = cprman->regs + base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) debugfs_create_regset32("regdump", S_IRUGO, dentry, regset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct bcm2835_pll_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u32 cm_ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u32 a2w_ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u32 frac_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) u32 ana_reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u32 reference_enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* Bit in CM_LOCK to indicate when the PLL has locked. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u32 lock_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) const struct bcm2835_pll_ana_bits *ana;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) unsigned long min_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) unsigned long max_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * Highest rate for the VCO before we have to use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * pre-divide-by-2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) unsigned long max_fb_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct bcm2835_pll_ana_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u32 mask0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) u32 set0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u32 mask1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u32 set1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) u32 mask3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u32 set3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u32 fb_prediv_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static const struct bcm2835_pll_ana_bits bcm2835_ana_default = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .mask0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .set0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .mask1 = A2W_PLL_KI_MASK | A2W_PLL_KP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .set1 = (2 << A2W_PLL_KI_SHIFT) | (8 << A2W_PLL_KP_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .mask3 = A2W_PLL_KA_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .set3 = (2 << A2W_PLL_KA_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .fb_prediv_mask = BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static const struct bcm2835_pll_ana_bits bcm2835_ana_pllh = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .mask0 = A2W_PLLH_KA_MASK | A2W_PLLH_KI_LOW_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .set0 = (2 << A2W_PLLH_KA_SHIFT) | (2 << A2W_PLLH_KI_LOW_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .mask1 = A2W_PLLH_KI_HIGH_MASK | A2W_PLLH_KP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .set1 = (6 << A2W_PLLH_KP_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .mask3 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .set3 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .fb_prediv_mask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct bcm2835_pll_divider_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) const char *source_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) u32 cm_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u32 a2w_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) u32 load_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) u32 hold_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u32 fixed_divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct bcm2835_clock_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) const char *const *parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) int num_mux_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* Bitmap encoding which parents accept rate change propagation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) unsigned int set_rate_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u32 ctl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u32 div_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* Number of integer bits in the divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u32 int_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* Number of fractional bits in the divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u32 frac_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) bool is_vpu_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) bool is_mash_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) bool low_jitter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u32 tcnt_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct bcm2835_gate_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) const char *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) u32 ctl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct bcm2835_pll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct bcm2835_cprman *cprman;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) const struct bcm2835_pll_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static int bcm2835_pll_is_on(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct bcm2835_cprman *cprman = pll->cprman;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) const struct bcm2835_pll_data *data = pll->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return cprman_read(cprman, data->a2w_ctrl_reg) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) A2W_PLL_CTRL_PRST_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static u32 bcm2835_pll_get_prediv_mask(struct bcm2835_cprman *cprman,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) const struct bcm2835_pll_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * On BCM2711 there isn't a pre-divisor available in the PLL feedback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * loop. Bits 13:14 of ANA1 (PLLA,PLLB,PLLC,PLLD) have been re-purposed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * for to for VCO RANGE bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (cprman->soc & SOC_BCM2711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return data->ana->fb_prediv_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) unsigned long parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) u32 *ndiv, u32 *fdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) u64 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) div = (u64)rate << A2W_PLL_FRAC_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) do_div(div, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) *ndiv = div >> A2W_PLL_FRAC_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) *fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) u32 ndiv, u32 fdiv, u32 pdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) u64 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (pdiv == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) rate = (u64)parent_rate * ((ndiv << A2W_PLL_FRAC_BITS) + fdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) do_div(rate, pdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return rate >> A2W_PLL_FRAC_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static long bcm2835_pll_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) const struct bcm2835_pll_data *data = pll->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) u32 ndiv, fdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) rate = clamp(rate, data->min_rate, data->max_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) bcm2835_pll_choose_ndiv_and_fdiv(rate, *parent_rate, &ndiv, &fdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return bcm2835_pll_rate_from_divisors(*parent_rate, ndiv, fdiv, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static unsigned long bcm2835_pll_get_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct bcm2835_cprman *cprman = pll->cprman;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) const struct bcm2835_pll_data *data = pll->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u32 a2wctrl = cprman_read(cprman, data->a2w_ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) u32 ndiv, pdiv, fdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) bool using_prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (parent_rate == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ndiv = (a2wctrl & A2W_PLL_CTRL_NDIV_MASK) >> A2W_PLL_CTRL_NDIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) pdiv = (a2wctrl & A2W_PLL_CTRL_PDIV_MASK) >> A2W_PLL_CTRL_PDIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) using_prediv = cprman_read(cprman, data->ana_reg_base + 4) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) bcm2835_pll_get_prediv_mask(cprman, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (using_prediv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ndiv *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) fdiv *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static void bcm2835_pll_off(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct bcm2835_cprman *cprman = pll->cprman;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) const struct bcm2835_pll_data *data = pll->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) spin_lock(&cprman->regs_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) cprman_write(cprman, data->a2w_ctrl_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) cprman_read(cprman, data->a2w_ctrl_reg) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) A2W_PLL_CTRL_PWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) spin_unlock(&cprman->regs_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static int bcm2835_pll_on(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct bcm2835_cprman *cprman = pll->cprman;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) const struct bcm2835_pll_data *data = pll->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) ktime_t timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) cprman_write(cprman, data->a2w_ctrl_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) cprman_read(cprman, data->a2w_ctrl_reg) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ~A2W_PLL_CTRL_PWRDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* Take the PLL out of reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) spin_lock(&cprman->regs_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) cprman_write(cprman, data->cm_ctrl_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) spin_unlock(&cprman->regs_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /* Wait for the PLL to lock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (ktime_after(ktime_get(), timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) dev_err(cprman->dev, "%s: couldn't lock PLL\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) clk_hw_get_name(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) cprman_write(cprman, data->a2w_ctrl_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) cprman_read(cprman, data->a2w_ctrl_reg) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) A2W_PLL_CTRL_PRST_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) bcm2835_pll_write_ana(struct bcm2835_cprman *cprman, u32 ana_reg_base, u32 *ana)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * ANA register setup is done as a series of writes to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * ANA3-ANA0, in that order. This lets us write all 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * registers as a single cycle of the serdes interface (taking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * 100 xosc clocks), whereas if we were to update ana0, 1, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * 3 individually through their partial-write registers, each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * would be their own serdes cycle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) for (i = 3; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) cprman_write(cprman, ana_reg_base + i * 4, ana[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static int bcm2835_pll_set_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) unsigned long rate, unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct bcm2835_cprman *cprman = pll->cprman;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) const struct bcm2835_pll_data *data = pll->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) u32 prediv_mask = bcm2835_pll_get_prediv_mask(cprman, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) bool was_using_prediv, use_fb_prediv, do_ana_setup_first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) u32 ndiv, fdiv, a2w_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) u32 ana[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (rate > data->max_fb_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) use_fb_prediv = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) rate /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) use_fb_prediv = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) bcm2835_pll_choose_ndiv_and_fdiv(rate, parent_rate, &ndiv, &fdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) for (i = 3; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ana[i] = cprman_read(cprman, data->ana_reg_base + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) was_using_prediv = ana[1] & prediv_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ana[0] &= ~data->ana->mask0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ana[0] |= data->ana->set0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ana[1] &= ~data->ana->mask1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) ana[1] |= data->ana->set1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) ana[3] &= ~data->ana->mask3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ana[3] |= data->ana->set3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (was_using_prediv && !use_fb_prediv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) ana[1] &= ~prediv_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) do_ana_setup_first = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) } else if (!was_using_prediv && use_fb_prediv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) ana[1] |= prediv_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) do_ana_setup_first = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) do_ana_setup_first = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* Unmask the reference clock from the oscillator. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) spin_lock(&cprman->regs_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) cprman_write(cprman, A2W_XOSC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) cprman_read(cprman, A2W_XOSC_CTRL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) data->reference_enable_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) spin_unlock(&cprman->regs_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (do_ana_setup_first)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /* Set the PLL multiplier from the oscillator. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) cprman_write(cprman, data->frac_reg, fdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) a2w_ctl = cprman_read(cprman, data->a2w_ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) a2w_ctl &= ~A2W_PLL_CTRL_NDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) a2w_ctl |= ndiv << A2W_PLL_CTRL_NDIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) a2w_ctl &= ~A2W_PLL_CTRL_PDIV_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) a2w_ctl |= 1 << A2W_PLL_CTRL_PDIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) cprman_write(cprman, data->a2w_ctrl_reg, a2w_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (!do_ana_setup_first)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static void bcm2835_pll_debug_init(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct dentry *dentry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct bcm2835_cprman *cprman = pll->cprman;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) const struct bcm2835_pll_data *data = pll->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct debugfs_reg32 *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (!regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) regs[0].name = "cm_ctrl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) regs[0].offset = data->cm_ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) regs[1].name = "a2w_ctrl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) regs[1].offset = data->a2w_ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) regs[2].name = "frac";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) regs[2].offset = data->frac_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) regs[3].name = "ana0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) regs[3].offset = data->ana_reg_base + 0 * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) regs[4].name = "ana1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) regs[4].offset = data->ana_reg_base + 1 * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) regs[5].name = "ana2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) regs[5].offset = data->ana_reg_base + 2 * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) regs[6].name = "ana3";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) regs[6].offset = data->ana_reg_base + 3 * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) bcm2835_debugfs_regset(cprman, 0, regs, 7, dentry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static const struct clk_ops bcm2835_pll_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .is_prepared = bcm2835_pll_is_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .prepare = bcm2835_pll_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .unprepare = bcm2835_pll_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .recalc_rate = bcm2835_pll_get_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .set_rate = bcm2835_pll_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .round_rate = bcm2835_pll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .debug_init = bcm2835_pll_debug_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct bcm2835_pll_divider {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct clk_divider div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) struct bcm2835_cprman *cprman;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) const struct bcm2835_pll_divider_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static struct bcm2835_pll_divider *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) bcm2835_pll_divider_from_hw(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return container_of(hw, struct bcm2835_pll_divider, div.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static int bcm2835_pll_divider_is_on(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct bcm2835_cprman *cprman = divider->cprman;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) const struct bcm2835_pll_divider_data *data = divider->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static long bcm2835_pll_divider_round_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return clk_divider_ops.round_rate(hw, rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return clk_divider_ops.recalc_rate(hw, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static void bcm2835_pll_divider_off(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct bcm2835_cprman *cprman = divider->cprman;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) const struct bcm2835_pll_divider_data *data = divider->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) spin_lock(&cprman->regs_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) cprman_write(cprman, data->cm_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) (cprman_read(cprman, data->cm_reg) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ~data->load_mask) | data->hold_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) cprman_write(cprman, data->a2w_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) cprman_read(cprman, data->a2w_reg) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) A2W_PLL_CHANNEL_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) spin_unlock(&cprman->regs_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static int bcm2835_pll_divider_on(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) struct bcm2835_cprman *cprman = divider->cprman;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) const struct bcm2835_pll_divider_data *data = divider->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) spin_lock(&cprman->regs_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) cprman_write(cprman, data->a2w_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) cprman_read(cprman, data->a2w_reg) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ~A2W_PLL_CHANNEL_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) cprman_write(cprman, data->cm_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) cprman_read(cprman, data->cm_reg) & ~data->hold_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) spin_unlock(&cprman->regs_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static int bcm2835_pll_divider_set_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct bcm2835_cprman *cprman = divider->cprman;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) const struct bcm2835_pll_divider_data *data = divider->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) u32 cm, div, max_div = 1 << A2W_PLL_DIV_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) div = DIV_ROUND_UP_ULL(parent_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) div = min(div, max_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (div == max_div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) div = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) cprman_write(cprman, data->a2w_reg, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) cm = cprman_read(cprman, data->cm_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) cprman_write(cprman, data->cm_reg, cm | data->load_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) cprman_write(cprman, data->cm_reg, cm & ~data->load_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static void bcm2835_pll_divider_debug_init(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct dentry *dentry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) struct bcm2835_cprman *cprman = divider->cprman;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) const struct bcm2835_pll_divider_data *data = divider->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) struct debugfs_reg32 *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (!regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) regs[0].name = "cm";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) regs[0].offset = data->cm_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) regs[1].name = "a2w";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) regs[1].offset = data->a2w_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) bcm2835_debugfs_regset(cprman, 0, regs, 2, dentry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static const struct clk_ops bcm2835_pll_divider_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .is_prepared = bcm2835_pll_divider_is_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .prepare = bcm2835_pll_divider_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .unprepare = bcm2835_pll_divider_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .recalc_rate = bcm2835_pll_divider_get_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .set_rate = bcm2835_pll_divider_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .round_rate = bcm2835_pll_divider_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .debug_init = bcm2835_pll_divider_debug_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) * The CM dividers do fixed-point division, so we can't use the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * generic integer divider code like the PLL dividers do (and we can't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * fake it by having some fixed shifts preceding it in the clock tree,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * because we'd run out of bits in a 32-bit unsigned long).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) struct bcm2835_clock {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct bcm2835_cprman *cprman;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) const struct bcm2835_clock_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static struct bcm2835_clock *bcm2835_clock_from_hw(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return container_of(hw, struct bcm2835_clock, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static int bcm2835_clock_is_on(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) struct bcm2835_cprman *cprman = clock->cprman;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) const struct bcm2835_clock_data *data = clock->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static u32 bcm2835_clock_choose_div(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) const struct bcm2835_clock_data *data = clock->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) u32 unused_frac_mask =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) u64 temp = (u64)parent_rate << CM_DIV_FRAC_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) u64 rem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) u32 div, mindiv, maxdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) rem = do_div(temp, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) div = temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) div &= ~unused_frac_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /* different clamping limits apply for a mash clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (data->is_mash_clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /* clamp to min divider of 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) mindiv = 2 << CM_DIV_FRAC_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* clamp to the highest possible integer divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /* clamp to min divider of 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) mindiv = 1 << CM_DIV_FRAC_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) /* clamp to the highest possible fractional divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) CM_DIV_FRAC_BITS - data->frac_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) /* apply the clamping limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) div = max_t(u32, div, mindiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) div = min_t(u32, div, maxdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) return div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) static long bcm2835_clock_rate_from_divisor(struct bcm2835_clock *clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) unsigned long parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) u32 div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) const struct bcm2835_clock_data *data = clock->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) u64 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (data->int_bits == 0 && data->frac_bits == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) return parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * The divisor is a 12.12 fixed point field, but only some of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) * the bits are populated in any given clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) div >>= CM_DIV_FRAC_BITS - data->frac_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) div &= (1 << (data->int_bits + data->frac_bits)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (div == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) temp = (u64)parent_rate << data->frac_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) do_div(temp, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) return temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) struct bcm2835_cprman *cprman = clock->cprman;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) const struct bcm2835_clock_data *data = clock->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) u32 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (data->int_bits == 0 && data->frac_bits == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) return parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) div = cprman_read(cprman, data->div_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) return bcm2835_clock_rate_from_divisor(clock, parent_rate, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) struct bcm2835_cprman *cprman = clock->cprman;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) const struct bcm2835_clock_data *data = clock->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) ktime_t timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (ktime_after(ktime_get(), timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) dev_err(cprman->dev, "%s: couldn't lock PLL\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) clk_hw_get_name(&clock->hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) static void bcm2835_clock_off(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) struct bcm2835_cprman *cprman = clock->cprman;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) const struct bcm2835_clock_data *data = clock->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) spin_lock(&cprman->regs_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) cprman_write(cprman, data->ctl_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) spin_unlock(&cprman->regs_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /* BUSY will remain high until the divider completes its cycle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) bcm2835_clock_wait_busy(clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static int bcm2835_clock_on(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) struct bcm2835_cprman *cprman = clock->cprman;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) const struct bcm2835_clock_data *data = clock->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) spin_lock(&cprman->regs_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) cprman_write(cprman, data->ctl_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) cprman_read(cprman, data->ctl_reg) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) CM_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) CM_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) spin_unlock(&cprman->regs_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) /* Debug code to measure the clock once it's turned on to see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) * if it's ticking at the rate we expect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (data->tcnt_mux && false) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) dev_info(cprman->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) "clk %s: rate %ld, measure %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) data->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) clk_hw_get_rate(hw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) bcm2835_measure_tcnt_mux(cprman, data->tcnt_mux));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) static int bcm2835_clock_set_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) unsigned long rate, unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) struct bcm2835_cprman *cprman = clock->cprman;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) const struct bcm2835_clock_data *data = clock->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) u32 div = bcm2835_clock_choose_div(hw, rate, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) u32 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) spin_lock(&cprman->regs_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) * Setting up frac support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) * In principle it is recommended to stop/start the clock first,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) * but as we set CLK_SET_RATE_GATE during registration of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) * clock this requirement should be take care of by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) * clk-framework.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) cprman_write(cprman, data->ctl_reg, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) cprman_write(cprman, data->div_reg, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) spin_unlock(&cprman->regs_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) bcm2835_clk_is_pllc(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (!hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) return strncmp(clk_hw_get_name(hw), "pllc", 4) == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) static unsigned long bcm2835_clock_choose_div_and_prate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) int parent_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) u32 *div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) unsigned long *prate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) unsigned long *avgrate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) struct bcm2835_cprman *cprman = clock->cprman;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) const struct bcm2835_clock_data *data = clock->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) unsigned long best_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) u32 curdiv, mindiv, maxdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) struct clk_hw *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) parent = clk_hw_get_parent_by_index(hw, parent_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) if (!(BIT(parent_idx) & data->set_rate_parent)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) *prate = clk_hw_get_rate(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) *div = bcm2835_clock_choose_div(hw, rate, *prate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) *avgrate = bcm2835_clock_rate_from_divisor(clock, *prate, *div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (data->low_jitter && (*div & CM_DIV_FRAC_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) unsigned long high, low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) u32 int_div = *div & ~CM_DIV_FRAC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) high = bcm2835_clock_rate_from_divisor(clock, *prate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) int_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) int_div += CM_DIV_FRAC_MASK + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) low = bcm2835_clock_rate_from_divisor(clock, *prate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) int_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) * Return a value which is the maximum deviation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) * below the ideal rate, for use as a metric.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) return *avgrate - max(*avgrate - low, high - *avgrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) return *avgrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if (data->frac_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) dev_warn(cprman->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) "frac bits are not used when propagating rate change");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) /* clamp to min divider of 2 if we're dealing with a mash clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) mindiv = data->is_mash_clock ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) maxdiv = BIT(data->int_bits) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) /* TODO: Be smart, and only test a subset of the available divisors. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) for (curdiv = mindiv; curdiv <= maxdiv; curdiv++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) unsigned long tmp_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) tmp_rate = clk_hw_round_rate(parent, rate * curdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) tmp_rate /= curdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (curdiv == mindiv ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) (tmp_rate > best_rate && tmp_rate <= rate))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) best_rate = tmp_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if (best_rate == rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) *div = curdiv << CM_DIV_FRAC_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) *prate = curdiv * best_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) *avgrate = best_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) return best_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) static int bcm2835_clock_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) struct clk_hw *parent, *best_parent = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) bool current_parent_is_pllc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) unsigned long rate, best_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) unsigned long prate, best_prate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) unsigned long avgrate, best_avgrate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) size_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) u32 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) current_parent_is_pllc = bcm2835_clk_is_pllc(clk_hw_get_parent(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) * Select parent clock that results in the closest but lower rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) for (i = 0; i < clk_hw_get_num_parents(hw); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) parent = clk_hw_get_parent_by_index(hw, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (!parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) * Don't choose a PLLC-derived clock as our parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) * unless it had been manually set that way. PLLC's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) * frequency gets adjusted by the firmware due to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) * over-temp or under-voltage conditions, without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) * prior notification to our clock consumer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) if (bcm2835_clk_is_pllc(parent) && !current_parent_is_pllc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) rate = bcm2835_clock_choose_div_and_prate(hw, i, req->rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) &div, &prate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) &avgrate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) if (abs(req->rate - rate) < abs(req->rate - best_rate)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) best_parent = parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) best_prate = prate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) best_rate = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) best_avgrate = avgrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) if (!best_parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) req->best_parent_hw = best_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) req->best_parent_rate = best_prate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) req->rate = best_avgrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) static int bcm2835_clock_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) struct bcm2835_cprman *cprman = clock->cprman;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) const struct bcm2835_clock_data *data = clock->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) u8 src = (index << CM_SRC_SHIFT) & CM_SRC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) cprman_write(cprman, data->ctl_reg, src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) static u8 bcm2835_clock_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) struct bcm2835_cprman *cprman = clock->cprman;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) const struct bcm2835_clock_data *data = clock->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) u32 src = cprman_read(cprman, data->ctl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) return (src & CM_SRC_MASK) >> CM_SRC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) static const struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .name = "ctl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .name = "div",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .offset = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) static void bcm2835_clock_debug_init(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) struct dentry *dentry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) struct bcm2835_cprman *cprman = clock->cprman;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) const struct bcm2835_clock_data *data = clock->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) bcm2835_debugfs_regset(cprman, data->ctl_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) bcm2835_debugfs_clock_reg32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) ARRAY_SIZE(bcm2835_debugfs_clock_reg32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) dentry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) static const struct clk_ops bcm2835_clock_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .is_prepared = bcm2835_clock_is_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .prepare = bcm2835_clock_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .unprepare = bcm2835_clock_off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .recalc_rate = bcm2835_clock_get_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .set_rate = bcm2835_clock_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .determine_rate = bcm2835_clock_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .set_parent = bcm2835_clock_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .get_parent = bcm2835_clock_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .debug_init = bcm2835_clock_debug_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) static int bcm2835_vpu_clock_is_on(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) * The VPU clock can never be disabled (it doesn't have an ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) * bit), so it gets its own set of clock ops.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) static const struct clk_ops bcm2835_vpu_clock_clk_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .is_prepared = bcm2835_vpu_clock_is_on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .recalc_rate = bcm2835_clock_get_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) .set_rate = bcm2835_clock_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) .determine_rate = bcm2835_clock_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) .set_parent = bcm2835_clock_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .get_parent = bcm2835_clock_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) .debug_init = bcm2835_clock_debug_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) const void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) const struct bcm2835_pll_data *pll_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) struct bcm2835_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) memset(&init, 0, sizeof(init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) /* All of the PLLs derive from the external oscillator. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) init.parent_names = &cprman->real_parent_names[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) init.name = pll_data->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) init.ops = &bcm2835_pll_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) init.flags = pll_data->flags | CLK_IGNORE_UNUSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) pll = kzalloc(sizeof(*pll), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) if (!pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) pll->cprman = cprman;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) pll->data = pll_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) pll->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) ret = devm_clk_hw_register(cprman->dev, &pll->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) return &pll->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) static struct clk_hw *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) bcm2835_register_pll_divider(struct bcm2835_cprman *cprman,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) const void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) const struct bcm2835_pll_divider_data *divider_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) struct bcm2835_pll_divider *divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) const char *divider_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) if (divider_data->fixed_divider != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) "%s_prediv", divider_data->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) if (!divider_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) divider_name = divider_data->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) memset(&init, 0, sizeof(init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) init.parent_names = ÷r_data->source_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) init.name = divider_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) init.ops = &bcm2835_pll_divider_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) init.flags = divider_data->flags | CLK_IGNORE_UNUSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) if (!divider)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) divider->div.reg = cprman->regs + divider_data->a2w_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) divider->div.shift = A2W_PLL_DIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) divider->div.width = A2W_PLL_DIV_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) divider->div.lock = &cprman->regs_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) divider->div.hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) divider->div.table = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) divider->cprman = cprman;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) divider->data = divider_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) ret = devm_clk_hw_register(cprman->dev, ÷r->div.hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) * PLLH's channels have a fixed divide by 10 afterwards, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) * is what our consumers are actually using.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) if (divider_data->fixed_divider != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) return clk_hw_register_fixed_factor(cprman->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) divider_data->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) divider_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) divider_data->fixed_divider);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) return ÷r->div.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) const void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) const struct bcm2835_clock_data *clock_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) struct bcm2835_clock *clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) const char *parents[1 << CM_SRC_BITS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) size_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) * Replace our strings referencing parent clocks with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) * actual clock-output-name of the parent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) for (i = 0; i < clock_data->num_mux_parents; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) parents[i] = clock_data->parents[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) ret = match_string(cprman_parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) ARRAY_SIZE(cprman_parent_names),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) parents[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (ret >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) parents[i] = cprman->real_parent_names[ret];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) memset(&init, 0, sizeof(init));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) init.parent_names = parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) init.num_parents = clock_data->num_mux_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) init.name = clock_data->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) init.flags = clock_data->flags | CLK_IGNORE_UNUSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) * Pass the CLK_SET_RATE_PARENT flag if we are allowed to propagate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) * rate changes on at least of the parents.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) if (clock_data->set_rate_parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) init.flags |= CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) if (clock_data->is_vpu_clock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) init.ops = &bcm2835_vpu_clock_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) init.ops = &bcm2835_clock_clk_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) init.flags |= CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) /* If the clock wasn't actually enabled at boot, it's not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) * critical.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) if (!(cprman_read(cprman, clock_data->ctl_reg) & CM_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) init.flags &= ~CLK_IS_CRITICAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) clock = devm_kzalloc(cprman->dev, sizeof(*clock), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (!clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) clock->cprman = cprman;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) clock->data = clock_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) clock->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) ret = devm_clk_hw_register(cprman->dev, &clock->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) return &clock->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) static struct clk_hw *bcm2835_register_gate(struct bcm2835_cprman *cprman,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) const void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) const struct bcm2835_gate_data *gate_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) return clk_hw_register_gate(cprman->dev, gate_data->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) gate_data->parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) cprman->regs + gate_data->ctl_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) CM_GATE_BIT, 0, &cprman->regs_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) struct bcm2835_clk_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) struct clk_hw *(*clk_register)(struct bcm2835_cprman *cprman,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) const void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) unsigned int supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) const void *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) /* assignment helper macros for different clock types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) #define _REGISTER(f, s, ...) { .clk_register = f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) .supported = s, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) .data = __VA_ARGS__ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) #define REGISTER_PLL(s, ...) _REGISTER(&bcm2835_register_pll, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) s, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) &(struct bcm2835_pll_data) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) {__VA_ARGS__})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) #define REGISTER_PLL_DIV(s, ...) _REGISTER(&bcm2835_register_pll_divider, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) s, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) &(struct bcm2835_pll_divider_data) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) {__VA_ARGS__})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) #define REGISTER_CLK(s, ...) _REGISTER(&bcm2835_register_clock, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) s, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) &(struct bcm2835_clock_data) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) {__VA_ARGS__})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) #define REGISTER_GATE(s, ...) _REGISTER(&bcm2835_register_gate, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) s, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) &(struct bcm2835_gate_data) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) {__VA_ARGS__})
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) /* parent mux arrays plus helper macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) /* main oscillator parent mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) static const char *const bcm2835_clock_osc_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) "gnd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) "xosc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) "testdebug0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) "testdebug1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) #define REGISTER_OSC_CLK(s, ...) REGISTER_CLK( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) s, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .parents = bcm2835_clock_osc_parents, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) __VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) /* main peripherial parent mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) static const char *const bcm2835_clock_per_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) "gnd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) "xosc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) "testdebug0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) "testdebug1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) "plla_per",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) "pllc_per",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) "plld_per",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) "pllh_aux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) #define REGISTER_PER_CLK(s, ...) REGISTER_CLK( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) s, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) .parents = bcm2835_clock_per_parents, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) __VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) * Restrict clock sources for the PCM peripheral to the oscillator and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) * PLLD_PER because other source may have varying rates or be switched
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) * off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) * Prevent other sources from being selected by replacing their names in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) * the list of potential parents with dummy entries (entry index is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) * significant).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) static const char *const bcm2835_pcm_per_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) "-",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) "xosc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) "-",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) "-",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) "-",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) "-",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) "plld_per",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) "-",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) #define REGISTER_PCM_CLK(s, ...) REGISTER_CLK( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) s, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .num_mux_parents = ARRAY_SIZE(bcm2835_pcm_per_parents), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .parents = bcm2835_pcm_per_parents, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) __VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) /* main vpu parent mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) static const char *const bcm2835_clock_vpu_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) "gnd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) "xosc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) "testdebug0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) "testdebug1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) "plla_core",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) "pllc_core0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) "plld_core",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) "pllh_aux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) "pllc_core1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) "pllc_core2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) #define REGISTER_VPU_CLK(s, ...) REGISTER_CLK( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) s, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .parents = bcm2835_clock_vpu_parents, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) __VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) * DSI parent clocks. The DSI byte/DDR/DDR2 clocks come from the DSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) * analog PHY. The _inv variants are generated internally to cprman,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) * but we don't use them so they aren't hooked up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) static const char *const bcm2835_clock_dsi0_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) "gnd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) "xosc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) "testdebug0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) "testdebug1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) "dsi0_ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) "dsi0_ddr_inv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) "dsi0_ddr2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) "dsi0_ddr2_inv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) "dsi0_byte",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) "dsi0_byte_inv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) static const char *const bcm2835_clock_dsi1_parents[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) "gnd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) "xosc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) "testdebug0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) "testdebug1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) "dsi1_ddr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) "dsi1_ddr_inv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) "dsi1_ddr2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) "dsi1_ddr2_inv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) "dsi1_byte",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) "dsi1_byte_inv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) #define REGISTER_DSI0_CLK(s, ...) REGISTER_CLK( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) s, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi0_parents), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) .parents = bcm2835_clock_dsi0_parents, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) __VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) #define REGISTER_DSI1_CLK(s, ...) REGISTER_CLK( \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) s, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi1_parents), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .parents = bcm2835_clock_dsi1_parents, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) __VA_ARGS__)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) * the real definition of all the pll, pll_dividers and clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) * these make use of the above REGISTER_* macros
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) static const struct bcm2835_clk_desc clk_desc_array[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) /* the PLL + PLL dividers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) * PLLA is the auxiliary PLL, used to drive the CCP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) * (Compact Camera Port 2) transmitter clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) * It is in the PX LDO power domain, which is on when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) * AUDIO domain is on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) [BCM2835_PLLA] = REGISTER_PLL(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) .name = "plla",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) .cm_ctrl_reg = CM_PLLA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) .a2w_ctrl_reg = A2W_PLLA_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) .frac_reg = A2W_PLLA_FRAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) .ana_reg_base = A2W_PLLA_ANA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .lock_mask = CM_LOCK_FLOCKA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .ana = &bcm2835_ana_default,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) .min_rate = 600000000u,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) .max_rate = 2400000000u,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) .max_fb_rate = BCM2835_MAX_FB_RATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) .name = "plla_core",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .source_pll = "plla",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) .cm_reg = CM_PLLA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .a2w_reg = A2W_PLLA_CORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) .load_mask = CM_PLLA_LOADCORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .hold_mask = CM_PLLA_HOLDCORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .fixed_divider = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .flags = CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) [BCM2835_PLLA_PER] = REGISTER_PLL_DIV(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) .name = "plla_per",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) .source_pll = "plla",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) .cm_reg = CM_PLLA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .a2w_reg = A2W_PLLA_PER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .load_mask = CM_PLLA_LOADPER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) .hold_mask = CM_PLLA_HOLDPER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) .fixed_divider = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .flags = CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .name = "plla_dsi0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .source_pll = "plla",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) .cm_reg = CM_PLLA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .a2w_reg = A2W_PLLA_DSI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .load_mask = CM_PLLA_LOADDSI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .hold_mask = CM_PLLA_HOLDDSI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) .fixed_divider = 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .name = "plla_ccp2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .source_pll = "plla",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .cm_reg = CM_PLLA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .a2w_reg = A2W_PLLA_CCP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) .load_mask = CM_PLLA_LOADCCP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) .hold_mask = CM_PLLA_HOLDCCP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .fixed_divider = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) .flags = CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) /* PLLB is used for the ARM's clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) [BCM2835_PLLB] = REGISTER_PLL(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) .name = "pllb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .cm_ctrl_reg = CM_PLLB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .a2w_ctrl_reg = A2W_PLLB_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .frac_reg = A2W_PLLB_FRAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .ana_reg_base = A2W_PLLB_ANA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .lock_mask = CM_LOCK_FLOCKB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .ana = &bcm2835_ana_default,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .min_rate = 600000000u,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) .max_rate = 3000000000u,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .max_fb_rate = BCM2835_MAX_FB_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .flags = CLK_GET_RATE_NOCACHE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) .name = "pllb_arm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) .source_pll = "pllb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .cm_reg = CM_PLLB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .a2w_reg = A2W_PLLB_ARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .load_mask = CM_PLLB_LOADARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) .hold_mask = CM_PLLB_HOLDARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .fixed_divider = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) * PLLC is the core PLL, used to drive the core VPU clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) * It is in the PX LDO power domain, which is on when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) * AUDIO domain is on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) [BCM2835_PLLC] = REGISTER_PLL(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .name = "pllc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) .cm_ctrl_reg = CM_PLLC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) .a2w_ctrl_reg = A2W_PLLC_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) .frac_reg = A2W_PLLC_FRAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .ana_reg_base = A2W_PLLC_ANA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .lock_mask = CM_LOCK_FLOCKC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) .ana = &bcm2835_ana_default,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) .min_rate = 600000000u,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) .max_rate = 3000000000u,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .max_fb_rate = BCM2835_MAX_FB_RATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) .name = "pllc_core0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) .source_pll = "pllc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) .cm_reg = CM_PLLC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) .a2w_reg = A2W_PLLC_CORE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) .load_mask = CM_PLLC_LOADCORE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) .hold_mask = CM_PLLC_HOLDCORE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) .fixed_divider = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) .flags = CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) .name = "pllc_core1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) .source_pll = "pllc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) .cm_reg = CM_PLLC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .a2w_reg = A2W_PLLC_CORE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .load_mask = CM_PLLC_LOADCORE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) .hold_mask = CM_PLLC_HOLDCORE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) .fixed_divider = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) .flags = CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .name = "pllc_core2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) .source_pll = "pllc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) .cm_reg = CM_PLLC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) .a2w_reg = A2W_PLLC_CORE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) .load_mask = CM_PLLC_LOADCORE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) .hold_mask = CM_PLLC_HOLDCORE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .fixed_divider = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) .flags = CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) [BCM2835_PLLC_PER] = REGISTER_PLL_DIV(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) .name = "pllc_per",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) .source_pll = "pllc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) .cm_reg = CM_PLLC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) .a2w_reg = A2W_PLLC_PER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) .load_mask = CM_PLLC_LOADPER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) .hold_mask = CM_PLLC_HOLDPER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .fixed_divider = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .flags = CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) * PLLD is the display PLL, used to drive DSI display panels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) * It is in the PX LDO power domain, which is on when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) * AUDIO domain is on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) [BCM2835_PLLD] = REGISTER_PLL(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) .name = "plld",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) .cm_ctrl_reg = CM_PLLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) .a2w_ctrl_reg = A2W_PLLD_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .frac_reg = A2W_PLLD_FRAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .ana_reg_base = A2W_PLLD_ANA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) .lock_mask = CM_LOCK_FLOCKD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) .ana = &bcm2835_ana_default,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) .min_rate = 600000000u,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) .max_rate = 2400000000u,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) .max_fb_rate = BCM2835_MAX_FB_RATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) .name = "plld_core",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) .source_pll = "plld",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) .cm_reg = CM_PLLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) .a2w_reg = A2W_PLLD_CORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) .load_mask = CM_PLLD_LOADCORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) .hold_mask = CM_PLLD_HOLDCORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) .fixed_divider = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) .flags = CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) * VPU firmware assumes that PLLD_PER isn't disabled by the ARM core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) * Otherwise this could cause firmware lookups. That's why we mark
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) * it as critical.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) [BCM2835_PLLD_PER] = REGISTER_PLL_DIV(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) .name = "plld_per",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) .source_pll = "plld",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) .cm_reg = CM_PLLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) .a2w_reg = A2W_PLLD_PER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) .load_mask = CM_PLLD_LOADPER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) .hold_mask = CM_PLLD_HOLDPER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) .fixed_divider = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .name = "plld_dsi0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .source_pll = "plld",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .cm_reg = CM_PLLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) .a2w_reg = A2W_PLLD_DSI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) .load_mask = CM_PLLD_LOADDSI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) .hold_mask = CM_PLLD_HOLDDSI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) .fixed_divider = 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) .name = "plld_dsi1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) .source_pll = "plld",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .cm_reg = CM_PLLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) .a2w_reg = A2W_PLLD_DSI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .load_mask = CM_PLLD_LOADDSI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .hold_mask = CM_PLLD_HOLDDSI1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) .fixed_divider = 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) * PLLH is used to supply the pixel clock or the AUX clock for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) * TV encoder.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) * It is in the HDMI power domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) [BCM2835_PLLH] = REGISTER_PLL(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) SOC_BCM2835,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) "pllh",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) .cm_ctrl_reg = CM_PLLH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) .a2w_ctrl_reg = A2W_PLLH_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) .frac_reg = A2W_PLLH_FRAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .ana_reg_base = A2W_PLLH_ANA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) .lock_mask = CM_LOCK_FLOCKH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) .ana = &bcm2835_ana_pllh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) .min_rate = 600000000u,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) .max_rate = 3000000000u,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) .max_fb_rate = BCM2835_MAX_FB_RATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) SOC_BCM2835,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .name = "pllh_rcal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .source_pll = "pllh",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .cm_reg = CM_PLLH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .a2w_reg = A2W_PLLH_RCAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .load_mask = CM_PLLH_LOADRCAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) .hold_mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) .fixed_divider = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) .flags = CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) SOC_BCM2835,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) .name = "pllh_aux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .source_pll = "pllh",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .cm_reg = CM_PLLH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .a2w_reg = A2W_PLLH_AUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .load_mask = CM_PLLH_LOADAUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) .hold_mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) .fixed_divider = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) .flags = CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) SOC_BCM2835,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) .name = "pllh_pix",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) .source_pll = "pllh",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) .cm_reg = CM_PLLH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) .a2w_reg = A2W_PLLH_PIX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) .load_mask = CM_PLLH_LOADPIX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) .hold_mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) .fixed_divider = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) .flags = CLK_SET_RATE_PARENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) /* the clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) /* clocks with oscillator parent mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) /* One Time Programmable Memory clock. Maximum 10Mhz. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) [BCM2835_CLOCK_OTP] = REGISTER_OSC_CLK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) .name = "otp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) .ctl_reg = CM_OTPCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) .div_reg = CM_OTPDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) .int_bits = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) .frac_bits = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) .tcnt_mux = 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) * Used for a 1Mhz clock for the system clocksource, and also used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) * bythe watchdog timer and the camera pulse generator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) [BCM2835_CLOCK_TIMER] = REGISTER_OSC_CLK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .name = "timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) .ctl_reg = CM_TIMERCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) .div_reg = CM_TIMERDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) .int_bits = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) .frac_bits = 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) * Clock for the temperature sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) * Generally run at 2Mhz, max 5Mhz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) [BCM2835_CLOCK_TSENS] = REGISTER_OSC_CLK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .name = "tsens",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) .ctl_reg = CM_TSENSCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) .div_reg = CM_TSENSDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .int_bits = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .frac_bits = 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) [BCM2835_CLOCK_TEC] = REGISTER_OSC_CLK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) .name = "tec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) .ctl_reg = CM_TECCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) .div_reg = CM_TECDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) .int_bits = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) .frac_bits = 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) /* clocks with vpu parent mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) .name = "h264",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .ctl_reg = CM_H264CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) .div_reg = CM_H264DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) .int_bits = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) .frac_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) .tcnt_mux = 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) [BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) .name = "isp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) .ctl_reg = CM_ISPCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) .div_reg = CM_ISPDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) .int_bits = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) .frac_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) .tcnt_mux = 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) * Secondary SDRAM clock. Used for low-voltage modes when the PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) * in the SDRAM controller can't be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) [BCM2835_CLOCK_SDRAM] = REGISTER_VPU_CLK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) .name = "sdram",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) .ctl_reg = CM_SDCCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) .div_reg = CM_SDCDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) .int_bits = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) .frac_bits = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) .tcnt_mux = 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) .name = "v3d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) .ctl_reg = CM_V3DCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .div_reg = CM_V3DDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) .int_bits = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) .frac_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) .tcnt_mux = 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) * VPU clock. This doesn't have an enable bit, since it drives
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) * the bus for everything else, and is special so it doesn't need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) * to be gated for rate changes. It is also known as "clk_audio"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) * in various hardware documentation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) [BCM2835_CLOCK_VPU] = REGISTER_VPU_CLK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) .name = "vpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) .ctl_reg = CM_VPUCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) .div_reg = CM_VPUDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) .int_bits = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) .frac_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) .is_vpu_clock = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) .tcnt_mux = 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) /* clocks with per parent mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .name = "aveo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) .ctl_reg = CM_AVEOCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) .div_reg = CM_AVEODIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) .int_bits = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) .frac_bits = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) .tcnt_mux = 38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) .name = "cam0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) .ctl_reg = CM_CAM0CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) .div_reg = CM_CAM0DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) .int_bits = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) .frac_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) .tcnt_mux = 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) .name = "cam1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) .ctl_reg = CM_CAM1CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) .div_reg = CM_CAM1DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) .int_bits = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) .frac_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) .tcnt_mux = 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) .name = "dft",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) .ctl_reg = CM_DFTCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) .div_reg = CM_DFTDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) .int_bits = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) .frac_bits = 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) [BCM2835_CLOCK_DPI] = REGISTER_PER_CLK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) .name = "dpi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) .ctl_reg = CM_DPICTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) .div_reg = CM_DPIDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) .int_bits = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) .frac_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) .tcnt_mux = 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) /* Arasan EMMC clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) .name = "emmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) .ctl_reg = CM_EMMCCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) .div_reg = CM_EMMCDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) .int_bits = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) .frac_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) .tcnt_mux = 39),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) /* EMMC2 clock (only available for BCM2711) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) [BCM2711_CLOCK_EMMC2] = REGISTER_PER_CLK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) SOC_BCM2711,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) .name = "emmc2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) .ctl_reg = CM_EMMC2CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) .div_reg = CM_EMMC2DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) .int_bits = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) .frac_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) .tcnt_mux = 42),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) /* General purpose (GPIO) clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) .name = "gp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) .ctl_reg = CM_GP0CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) .div_reg = CM_GP0DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) .int_bits = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) .frac_bits = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) .is_mash_clock = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) .tcnt_mux = 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) .name = "gp1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) .ctl_reg = CM_GP1CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) .div_reg = CM_GP1DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) .int_bits = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) .frac_bits = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) .flags = CLK_IS_CRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) .is_mash_clock = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .tcnt_mux = 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) .name = "gp2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) .ctl_reg = CM_GP2CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) .div_reg = CM_GP2DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) .int_bits = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) .frac_bits = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) .flags = CLK_IS_CRITICAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) /* HDMI state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) .name = "hsm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) .ctl_reg = CM_HSMCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) .div_reg = CM_HSMDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) .int_bits = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) .frac_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) .tcnt_mux = 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) [BCM2835_CLOCK_PCM] = REGISTER_PCM_CLK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) .name = "pcm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) .ctl_reg = CM_PCMCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) .div_reg = CM_PCMDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) .int_bits = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) .frac_bits = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) .is_mash_clock = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) .low_jitter = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) .tcnt_mux = 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) .name = "pwm",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) .ctl_reg = CM_PWMCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) .div_reg = CM_PWMDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) .int_bits = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) .frac_bits = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) .is_mash_clock = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) .tcnt_mux = 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) .name = "slim",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) .ctl_reg = CM_SLIMCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) .div_reg = CM_SLIMDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) .int_bits = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .frac_bits = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) .is_mash_clock = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) .tcnt_mux = 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) .name = "smi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) .ctl_reg = CM_SMICTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) .div_reg = CM_SMIDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) .int_bits = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) .frac_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) .tcnt_mux = 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) [BCM2835_CLOCK_UART] = REGISTER_PER_CLK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) .name = "uart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) .ctl_reg = CM_UARTCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) .div_reg = CM_UARTDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) .int_bits = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) .frac_bits = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) .tcnt_mux = 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) /* TV encoder clock. Only operating frequency is 108Mhz. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) .name = "vec",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) .ctl_reg = CM_VECCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) .div_reg = CM_VECDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) .int_bits = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) .frac_bits = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) * Allow rate change propagation only on PLLH_AUX which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) * assigned index 7 in the parent array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) .set_rate_parent = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) .tcnt_mux = 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) /* dsi clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) .name = "dsi0e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) .ctl_reg = CM_DSI0ECTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) .div_reg = CM_DSI0EDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) .int_bits = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) .frac_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) .tcnt_mux = 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) .name = "dsi1e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) .ctl_reg = CM_DSI1ECTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) .div_reg = CM_DSI1EDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) .int_bits = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) .frac_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) .tcnt_mux = 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) [BCM2835_CLOCK_DSI0P] = REGISTER_DSI0_CLK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) .name = "dsi0p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) .ctl_reg = CM_DSI0PCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) .div_reg = CM_DSI0PDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) .int_bits = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) .frac_bits = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) .tcnt_mux = 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) [BCM2835_CLOCK_DSI1P] = REGISTER_DSI1_CLK(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) .name = "dsi1p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) .ctl_reg = CM_DSI1PCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) .div_reg = CM_DSI1PDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) .int_bits = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) .frac_bits = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) .tcnt_mux = 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) /* the gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) * you have the debug bit set in the power manager, which we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) * don't bother exposing) are individual gates off of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) * non-stop vpu clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) SOC_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) .name = "peri_image",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) .parent = "vpu",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) .ctl_reg = CM_PERIICTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) * Permanently take a reference on the parent of the SDRAM clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) * While the SDRAM is being driven by its dedicated PLL most of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) * time, there is a little loop running in the firmware that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) * periodically switches the SDRAM to using our CM clock to do PVT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) * recalibration, with the assumption that the previously configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) * SDRAM parent is still enabled and running.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) static int bcm2835_mark_sdc_parent_critical(struct clk *sdc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) struct clk *parent = clk_get_parent(sdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) if (IS_ERR(parent))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) return PTR_ERR(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) return clk_prepare_enable(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) static int bcm2835_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) struct clk_hw **hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) struct bcm2835_cprman *cprman;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) const struct bcm2835_clk_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) const size_t asize = ARRAY_SIZE(clk_desc_array);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) const struct cprman_plat_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) size_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) pdata = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) cprman = devm_kzalloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) struct_size(cprman, onecell.hws, asize),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) if (!cprman)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) spin_lock_init(&cprman->regs_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) cprman->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) cprman->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) if (IS_ERR(cprman->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) return PTR_ERR(cprman->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) memcpy(cprman->real_parent_names, cprman_parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) sizeof(cprman_parent_names));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) of_clk_parent_fill(dev->of_node, cprman->real_parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) ARRAY_SIZE(cprman_parent_names));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) * Make sure the external oscillator has been registered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) * The other (DSI) clocks are not present on older device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) * trees, which we still need to support for backwards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) * compatibility.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) if (!cprman->real_parent_names[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) platform_set_drvdata(pdev, cprman);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) cprman->onecell.num = asize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) cprman->soc = pdata->soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) hws = cprman->onecell.hws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) for (i = 0; i < asize; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) desc = &clk_desc_array[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) if (desc->clk_register && desc->data &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) (desc->supported & pdata->soc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) hws[i] = desc->clk_register(cprman, desc->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) ret = bcm2835_mark_sdc_parent_critical(hws[BCM2835_CLOCK_SDRAM]->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) &cprman->onecell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) static const struct cprman_plat_data cprman_bcm2835_plat_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) .soc = SOC_BCM2835,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) static const struct cprman_plat_data cprman_bcm2711_plat_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) .soc = SOC_BCM2711,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) static const struct of_device_id bcm2835_clk_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) { .compatible = "brcm,bcm2835-cprman", .data = &cprman_bcm2835_plat_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) { .compatible = "brcm,bcm2711-cprman", .data = &cprman_bcm2711_plat_data },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) static struct platform_driver bcm2835_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) .name = "bcm2835-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) .of_match_table = bcm2835_clk_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) .probe = bcm2835_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) builtin_platform_driver(bcm2835_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) MODULE_DESCRIPTION("BCM2835 clock driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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