Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2015 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <dt-bindings/clock/bcm2835-aux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define BCM2835_AUXIRQ		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define BCM2835_AUXENB		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static int bcm2835_aux_clk_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	struct clk_hw_onecell_data *onecell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	const char *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	struct clk *parent_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	void __iomem *reg, *gate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	parent_clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	if (IS_ERR(parent_clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		return PTR_ERR(parent_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	parent = __clk_get_name(parent_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	reg = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	if (IS_ERR(reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		return PTR_ERR(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	onecell = devm_kmalloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 			       struct_size(onecell, hws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 					   BCM2835_AUX_CLOCK_COUNT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 			       GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	if (!onecell)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	onecell->num = BCM2835_AUX_CLOCK_COUNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	gate = reg + BCM2835_AUXENB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	onecell->hws[BCM2835_AUX_CLOCK_UART] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		clk_hw_register_gate(dev, "aux_uart", parent, 0, gate, 0, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	onecell->hws[BCM2835_AUX_CLOCK_SPI1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		clk_hw_register_gate(dev, "aux_spi1", parent, 0, gate, 1, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	onecell->hws[BCM2835_AUX_CLOCK_SPI2] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		clk_hw_register_gate(dev, "aux_spi2", parent, 0, gate, 2, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	return of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 				      onecell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static const struct of_device_id bcm2835_aux_clk_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	{ .compatible = "brcm,bcm2835-aux", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MODULE_DEVICE_TABLE(of, bcm2835_aux_clk_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static struct platform_driver bcm2835_aux_clk_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		.name = "bcm2835-aux-clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 		.of_match_table = bcm2835_aux_clk_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	.probe          = bcm2835_aux_clk_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) builtin_platform_driver(bcm2835_aux_clk_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MODULE_DESCRIPTION("BCM2835 auxiliary peripheral clock driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MODULE_LICENSE("GPL");