Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Copyright (C) 2013 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2013 Linaro Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "clk-kona.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "dt-bindings/clock/bcm281xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define BCM281XX_CCU_COMMON(_name, _ucase_name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	KONA_CCU_COMMON(BCM281XX, _name, _ucase_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* Root CCU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) static struct peri_clk_data frac_1m_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	.gate		= HW_SW_GATE(0x214, 16, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	.trig		= TRIGGER(0x0e04, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	.div		= FRAC_DIVIDER(0x0e00, 0, 22, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	.clocks		= CLOCKS("ref_crystal"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) static struct ccu_data root_ccu_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	BCM281XX_CCU_COMMON(root, ROOT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	.kona_clks	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 		[BCM281XX_ROOT_CCU_FRAC_1M] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 			KONA_CLK(root, frac_1m, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 		[BCM281XX_ROOT_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /* AON CCU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) static struct peri_clk_data hub_timer_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	.gate		= HW_SW_GATE(0x0414, 16, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	.clocks		= CLOCKS("bbl_32k",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 				 "frac_1m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 				 "dft_19_5m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	.sel		= SELECTOR(0x0a10, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	.trig		= TRIGGER(0x0a40, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static struct peri_clk_data pmu_bsc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	.gate		= HW_SW_GATE(0x0418, 16, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	.clocks		= CLOCKS("ref_crystal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 				 "pmu_bsc_var",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 				 "bbl_32k"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	.sel		= SELECTOR(0x0a04, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	.div		= DIVIDER(0x0a04, 3, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	.trig		= TRIGGER(0x0a40, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static struct peri_clk_data pmu_bsc_var_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	.clocks		= CLOCKS("var_312m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 				 "ref_312m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	.sel		= SELECTOR(0x0a00, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	.div		= DIVIDER(0x0a00, 4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	.trig		= TRIGGER(0x0a40, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) static struct ccu_data aon_ccu_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	BCM281XX_CCU_COMMON(aon, AON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	.kona_clks	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		[BCM281XX_AON_CCU_HUB_TIMER] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 			KONA_CLK(aon, hub_timer, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		[BCM281XX_AON_CCU_PMU_BSC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 			KONA_CLK(aon, pmu_bsc, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		[BCM281XX_AON_CCU_PMU_BSC_VAR] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 			KONA_CLK(aon, pmu_bsc_var, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		[BCM281XX_AON_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /* Hub CCU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static struct peri_clk_data tmon_1m_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	.gate		= HW_SW_GATE(0x04a4, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	.clocks		= CLOCKS("ref_crystal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 				 "frac_1m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	.sel		= SELECTOR(0x0e74, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	.trig		= TRIGGER(0x0e84, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static struct ccu_data hub_ccu_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	BCM281XX_CCU_COMMON(hub, HUB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	.kona_clks	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		[BCM281XX_HUB_CCU_TMON_1M] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 			KONA_CLK(hub, tmon_1m, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		[BCM281XX_HUB_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Master CCU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static struct peri_clk_data sdio1_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	.gate		= HW_SW_GATE(0x0358, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	.clocks		= CLOCKS("ref_crystal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 				 "var_52m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 				 "ref_52m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 				 "var_96m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 				 "ref_96m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	.sel		= SELECTOR(0x0a28, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	.div		= DIVIDER(0x0a28, 4, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	.trig		= TRIGGER(0x0afc, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static struct peri_clk_data sdio2_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.gate		= HW_SW_GATE(0x035c, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.clocks		= CLOCKS("ref_crystal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 				 "var_52m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 				 "ref_52m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 				 "var_96m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 				 "ref_96m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	.sel		= SELECTOR(0x0a2c, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	.div		= DIVIDER(0x0a2c, 4, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	.trig		= TRIGGER(0x0afc, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static struct peri_clk_data sdio3_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	.gate		= HW_SW_GATE(0x0364, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	.clocks		= CLOCKS("ref_crystal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 				 "var_52m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 				 "ref_52m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 				 "var_96m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 				 "ref_96m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	.sel		= SELECTOR(0x0a34, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	.div		= DIVIDER(0x0a34, 4, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	.trig		= TRIGGER(0x0afc, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static struct peri_clk_data sdio4_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.gate		= HW_SW_GATE(0x0360, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.clocks		= CLOCKS("ref_crystal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 				 "var_52m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 				 "ref_52m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 				 "var_96m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 				 "ref_96m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.sel		= SELECTOR(0x0a30, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.div		= DIVIDER(0x0a30, 4, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	.trig		= TRIGGER(0x0afc, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static struct peri_clk_data usb_ic_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.gate		= HW_SW_GATE(0x0354, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.clocks		= CLOCKS("ref_crystal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 				 "var_96m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 				 "ref_96m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.div		= FIXED_DIVIDER(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	.sel		= SELECTOR(0x0a24, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	.trig		= TRIGGER(0x0afc, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* also called usbh_48m */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static struct peri_clk_data hsic2_48m_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	.gate		= HW_SW_GATE(0x0370, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	.clocks		= CLOCKS("ref_crystal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 				 "var_96m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 				 "ref_96m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	.sel		= SELECTOR(0x0a38, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	.div		= FIXED_DIVIDER(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	.trig		= TRIGGER(0x0afc, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* also called usbh_12m */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static struct peri_clk_data hsic2_12m_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	.gate		= HW_SW_GATE(0x0370, 20, 4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	.div		= DIVIDER(0x0a38, 12, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.clocks		= CLOCKS("ref_crystal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 				 "var_96m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 				 "ref_96m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	.pre_div	= FIXED_DIVIDER(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	.sel		= SELECTOR(0x0a38, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.trig		= TRIGGER(0x0afc, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static struct ccu_data master_ccu_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	BCM281XX_CCU_COMMON(master, MASTER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.kona_clks	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		[BCM281XX_MASTER_CCU_SDIO1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			KONA_CLK(master, sdio1, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		[BCM281XX_MASTER_CCU_SDIO2] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			KONA_CLK(master, sdio2, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		[BCM281XX_MASTER_CCU_SDIO3] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			KONA_CLK(master, sdio3, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		[BCM281XX_MASTER_CCU_SDIO4] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			KONA_CLK(master, sdio4, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		[BCM281XX_MASTER_CCU_USB_IC] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			KONA_CLK(master, usb_ic, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		[BCM281XX_MASTER_CCU_HSIC2_48M] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			KONA_CLK(master, hsic2_48m, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		[BCM281XX_MASTER_CCU_HSIC2_12M] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			KONA_CLK(master, hsic2_12m, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		[BCM281XX_MASTER_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Slave CCU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static struct peri_clk_data uartb_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	.gate		= HW_SW_GATE(0x0400, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	.clocks		= CLOCKS("ref_crystal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 				 "var_156m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 				 "ref_156m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.sel		= SELECTOR(0x0a10, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.div		= FRAC_DIVIDER(0x0a10, 4, 12, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.trig		= TRIGGER(0x0afc, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static struct peri_clk_data uartb2_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	.gate		= HW_SW_GATE(0x0404, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	.clocks		= CLOCKS("ref_crystal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 				 "var_156m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 				 "ref_156m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	.sel		= SELECTOR(0x0a14, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	.div		= FRAC_DIVIDER(0x0a14, 4, 12, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	.trig		= TRIGGER(0x0afc, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static struct peri_clk_data uartb3_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	.gate		= HW_SW_GATE(0x0408, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	.clocks		= CLOCKS("ref_crystal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 				 "var_156m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 				 "ref_156m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	.sel		= SELECTOR(0x0a18, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	.div		= FRAC_DIVIDER(0x0a18, 4, 12, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	.trig		= TRIGGER(0x0afc, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static struct peri_clk_data uartb4_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	.gate		= HW_SW_GATE(0x0408, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	.clocks		= CLOCKS("ref_crystal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 				 "var_156m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 				 "ref_156m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.sel		= SELECTOR(0x0a1c, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.div		= FRAC_DIVIDER(0x0a1c, 4, 12, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.trig		= TRIGGER(0x0afc, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static struct peri_clk_data ssp0_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	.gate		= HW_SW_GATE(0x0410, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.clocks		= CLOCKS("ref_crystal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 				 "var_104m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 				 "ref_104m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 				 "var_96m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 				 "ref_96m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	.sel		= SELECTOR(0x0a20, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	.div		= DIVIDER(0x0a20, 4, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	.trig		= TRIGGER(0x0afc, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static struct peri_clk_data ssp2_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	.gate		= HW_SW_GATE(0x0418, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	.clocks		= CLOCKS("ref_crystal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 				 "var_104m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 				 "ref_104m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 				 "var_96m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 				 "ref_96m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	.sel		= SELECTOR(0x0a28, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	.div		= DIVIDER(0x0a28, 4, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	.trig		= TRIGGER(0x0afc, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static struct peri_clk_data bsc1_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	.gate		= HW_SW_GATE(0x0458, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	.clocks		= CLOCKS("ref_crystal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 				 "var_104m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 				 "ref_104m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 				 "var_13m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 				 "ref_13m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	.sel		= SELECTOR(0x0a64, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	.trig		= TRIGGER(0x0afc, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static struct peri_clk_data bsc2_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	.gate		= HW_SW_GATE(0x045c, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	.clocks	= CLOCKS("ref_crystal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 				 "var_104m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 				 "ref_104m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 				 "var_13m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 				 "ref_13m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	.sel		= SELECTOR(0x0a68, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	.trig		= TRIGGER(0x0afc, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static struct peri_clk_data bsc3_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	.gate		= HW_SW_GATE(0x0484, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	.clocks		= CLOCKS("ref_crystal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 				 "var_104m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 				 "ref_104m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 				 "var_13m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 				 "ref_13m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	.sel		= SELECTOR(0x0a84, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	.trig		= TRIGGER(0x0b00, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static struct peri_clk_data pwm_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	.gate		= HW_SW_GATE(0x0468, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	.clocks		= CLOCKS("ref_crystal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 				 "var_104m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	.sel		= SELECTOR(0x0a70, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	.div		= DIVIDER(0x0a70, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	.trig		= TRIGGER(0x0afc, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static struct ccu_data slave_ccu_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	BCM281XX_CCU_COMMON(slave, SLAVE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	.kona_clks	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		[BCM281XX_SLAVE_CCU_UARTB] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 			KONA_CLK(slave, uartb, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		[BCM281XX_SLAVE_CCU_UARTB2] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 			KONA_CLK(slave, uartb2, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		[BCM281XX_SLAVE_CCU_UARTB3] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 			KONA_CLK(slave, uartb3, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		[BCM281XX_SLAVE_CCU_UARTB4] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 			KONA_CLK(slave, uartb4, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		[BCM281XX_SLAVE_CCU_SSP0] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 			KONA_CLK(slave, ssp0, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		[BCM281XX_SLAVE_CCU_SSP2] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 			KONA_CLK(slave, ssp2, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		[BCM281XX_SLAVE_CCU_BSC1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 			KONA_CLK(slave, bsc1, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		[BCM281XX_SLAVE_CCU_BSC2] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			KONA_CLK(slave, bsc2, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		[BCM281XX_SLAVE_CCU_BSC3] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 			KONA_CLK(slave, bsc3, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		[BCM281XX_SLAVE_CCU_PWM] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 			KONA_CLK(slave, pwm, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		[BCM281XX_SLAVE_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* Device tree match table callback functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static void __init kona_dt_root_ccu_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	kona_dt_ccu_setup(&root_ccu_data, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static void __init kona_dt_aon_ccu_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	kona_dt_ccu_setup(&aon_ccu_data, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static void __init kona_dt_hub_ccu_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	kona_dt_ccu_setup(&hub_ccu_data, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static void __init kona_dt_master_ccu_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	kona_dt_ccu_setup(&master_ccu_data, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static void __init kona_dt_slave_ccu_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	kona_dt_ccu_setup(&slave_ccu_data, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) CLK_OF_DECLARE(bcm281xx_root_ccu, BCM281XX_DT_ROOT_CCU_COMPAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 			kona_dt_root_ccu_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) CLK_OF_DECLARE(bcm281xx_aon_ccu, BCM281XX_DT_AON_CCU_COMPAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 			kona_dt_aon_ccu_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) CLK_OF_DECLARE(bcm281xx_hub_ccu, BCM281XX_DT_HUB_CCU_COMPAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 			kona_dt_hub_ccu_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) CLK_OF_DECLARE(bcm281xx_master_ccu, BCM281XX_DT_MASTER_CCU_COMPAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 			kona_dt_master_ccu_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) CLK_OF_DECLARE(bcm281xx_slave_ccu, BCM281XX_DT_SLAVE_CCU_COMPAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 			kona_dt_slave_ccu_setup);