^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright 2020 Cerno
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/reset/reset-simple.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define DVP_HT_RPI_SW_INIT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define DVP_HT_RPI_MISC_CONFIG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define NR_CLOCKS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define NR_RESETS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct clk_dvp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct clk_hw_onecell_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct reset_simple_data reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static const struct clk_parent_data clk_dvp_parent = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .index = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static int clk_dvp_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct clk_hw_onecell_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct clk_dvp *dvp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) dvp = devm_kzalloc(&pdev->dev, sizeof(*dvp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) if (!dvp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) platform_set_drvdata(pdev, dvp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) dvp->data = devm_kzalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct_size(dvp->data, hws, NR_CLOCKS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (!dvp->data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) data = dvp->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) dvp->reset.rcdev.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) dvp->reset.rcdev.nr_resets = NR_RESETS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) dvp->reset.rcdev.ops = &reset_simple_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) dvp->reset.rcdev.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) dvp->reset.membase = base + DVP_HT_RPI_SW_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) spin_lock_init(&dvp->reset.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ret = devm_reset_controller_register(&pdev->dev, &dvp->reset.rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) data->hws[0] = clk_hw_register_gate_parent_data(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) "hdmi0-108MHz",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) &clk_dvp_parent, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) base + DVP_HT_RPI_MISC_CONFIG, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) CLK_GATE_SET_TO_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) &dvp->reset.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (IS_ERR(data->hws[0]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return PTR_ERR(data->hws[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) data->hws[1] = clk_hw_register_gate_parent_data(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) "hdmi1-108MHz",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) &clk_dvp_parent, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) base + DVP_HT_RPI_MISC_CONFIG, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) CLK_GATE_SET_TO_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) &dvp->reset.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (IS_ERR(data->hws[1])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ret = PTR_ERR(data->hws[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) goto unregister_clk0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) data->num = NR_CLOCKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) goto unregister_clk1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unregister_clk1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) clk_hw_unregister_gate(data->hws[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unregister_clk0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) clk_hw_unregister_gate(data->hws[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int clk_dvp_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct clk_dvp *dvp = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct clk_hw_onecell_data *data = dvp->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) clk_hw_unregister_gate(data->hws[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) clk_hw_unregister_gate(data->hws[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const struct of_device_id clk_dvp_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { .compatible = "brcm,brcm2711-dvp", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MODULE_DEVICE_TABLE(of, clk_dvp_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static struct platform_driver clk_dvp_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .probe = clk_dvp_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .remove = clk_dvp_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .name = "brcm2711-dvp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .of_match_table = clk_dvp_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) module_platform_driver(clk_dvp_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MODULE_AUTHOR("Maxime Ripard <maxime@cerno.tech>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MODULE_DESCRIPTION("BCM2711 DVP clock driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags