Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Copyright (C) 2014 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2014 Linaro Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "clk-kona.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "dt-bindings/clock/bcm21664.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define BCM21664_CCU_COMMON(_name, _capname) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	KONA_CCU_COMMON(BCM21664, _name, _capname)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* Root CCU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) static struct peri_clk_data frac_1m_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	.gate		= HW_SW_GATE(0x214, 16, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	.clocks		= CLOCKS("ref_crystal"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) static struct ccu_data root_ccu_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	BCM21664_CCU_COMMON(root, ROOT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	/* no policy control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	.kona_clks	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		[BCM21664_ROOT_CCU_FRAC_1M] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 			KONA_CLK(root, frac_1m, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		[BCM21664_ROOT_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /* AON CCU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static struct peri_clk_data hub_timer_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	.gate		= HW_SW_GATE(0x0414, 16, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	.hyst		= HYST(0x0414, 8, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	.clocks		= CLOCKS("bbl_32k",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 				 "frac_1m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 				 "dft_19_5m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	.sel		= SELECTOR(0x0a10, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	.trig		= TRIGGER(0x0a40, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static struct ccu_data aon_ccu_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	BCM21664_CCU_COMMON(aon, AON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	.policy		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		.enable		= CCU_LVM_EN(0x0034, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		.control	= CCU_POLICY_CTL(0x000c, 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	.kona_clks	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		[BCM21664_AON_CCU_HUB_TIMER] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 			KONA_CLK(aon, hub_timer, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		[BCM21664_AON_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /* Master CCU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static struct peri_clk_data sdio1_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	.gate		= HW_SW_GATE(0x0358, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	.clocks		= CLOCKS("ref_crystal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 				 "var_52m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 				 "ref_52m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 				 "var_96m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 				 "ref_96m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	.sel		= SELECTOR(0x0a28, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	.div		= DIVIDER(0x0a28, 4, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	.trig		= TRIGGER(0x0afc, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static struct peri_clk_data sdio2_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	.gate		= HW_SW_GATE(0x035c, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	.clocks		= CLOCKS("ref_crystal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 				 "var_52m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 				 "ref_52m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 				 "var_96m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 				 "ref_96m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	.sel		= SELECTOR(0x0a2c, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	.div		= DIVIDER(0x0a2c, 4, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.trig		= TRIGGER(0x0afc, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) static struct peri_clk_data sdio3_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	.gate		= HW_SW_GATE(0x0364, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	.clocks		= CLOCKS("ref_crystal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 				 "var_52m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 				 "ref_52m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 				 "var_96m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 				 "ref_96m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	.sel		= SELECTOR(0x0a34, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	.div		= DIVIDER(0x0a34, 4, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	.trig		= TRIGGER(0x0afc, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static struct peri_clk_data sdio4_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	.gate		= HW_SW_GATE(0x0360, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	.clocks		= CLOCKS("ref_crystal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 				 "var_52m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 				 "ref_52m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 				 "var_96m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 				 "ref_96m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	.sel		= SELECTOR(0x0a30, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	.div		= DIVIDER(0x0a30, 4, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	.trig		= TRIGGER(0x0afc, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static struct peri_clk_data sdio1_sleep_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	.clocks		= CLOCKS("ref_32k"),	/* Verify */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.gate		= HW_SW_GATE(0x0358, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static struct peri_clk_data sdio2_sleep_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	.clocks		= CLOCKS("ref_32k"),	/* Verify */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	.gate		= HW_SW_GATE(0x035c, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static struct peri_clk_data sdio3_sleep_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	.clocks		= CLOCKS("ref_32k"),	/* Verify */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	.gate		= HW_SW_GATE(0x0364, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static struct peri_clk_data sdio4_sleep_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	.clocks		= CLOCKS("ref_32k"),	/* Verify */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	.gate		= HW_SW_GATE(0x0360, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static struct ccu_data master_ccu_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	BCM21664_CCU_COMMON(master, MASTER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	.policy		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		.enable		= CCU_LVM_EN(0x0034, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		.control	= CCU_POLICY_CTL(0x000c, 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.kona_clks	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		[BCM21664_MASTER_CCU_SDIO1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			KONA_CLK(master, sdio1, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		[BCM21664_MASTER_CCU_SDIO2] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			KONA_CLK(master, sdio2, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		[BCM21664_MASTER_CCU_SDIO3] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			KONA_CLK(master, sdio3, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		[BCM21664_MASTER_CCU_SDIO4] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			KONA_CLK(master, sdio4, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		[BCM21664_MASTER_CCU_SDIO1_SLEEP] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			KONA_CLK(master, sdio1_sleep, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		[BCM21664_MASTER_CCU_SDIO2_SLEEP] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			KONA_CLK(master, sdio2_sleep, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		[BCM21664_MASTER_CCU_SDIO3_SLEEP] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			KONA_CLK(master, sdio3_sleep, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		[BCM21664_MASTER_CCU_SDIO4_SLEEP] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			KONA_CLK(master, sdio4_sleep, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		[BCM21664_MASTER_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Slave CCU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static struct peri_clk_data uartb_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	.gate		= HW_SW_GATE(0x0400, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	.clocks		= CLOCKS("ref_crystal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 				 "var_156m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 				 "ref_156m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	.sel		= SELECTOR(0x0a10, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	.div		= FRAC_DIVIDER(0x0a10, 4, 12, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.trig		= TRIGGER(0x0afc, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static struct peri_clk_data uartb2_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	.gate		= HW_SW_GATE(0x0404, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	.clocks		= CLOCKS("ref_crystal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 				 "var_156m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 				 "ref_156m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	.sel		= SELECTOR(0x0a14, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	.div		= FRAC_DIVIDER(0x0a14, 4, 12, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	.trig		= TRIGGER(0x0afc, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static struct peri_clk_data uartb3_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	.gate		= HW_SW_GATE(0x0408, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	.clocks		= CLOCKS("ref_crystal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 				 "var_156m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 				 "ref_156m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	.sel		= SELECTOR(0x0a18, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	.div		= FRAC_DIVIDER(0x0a18, 4, 12, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	.trig		= TRIGGER(0x0afc, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static struct peri_clk_data bsc1_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	.gate		= HW_SW_GATE(0x0458, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.clocks		= CLOCKS("ref_crystal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 				 "var_104m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 				 "ref_104m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 				 "var_13m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 				 "ref_13m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	.sel		= SELECTOR(0x0a64, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	.trig		= TRIGGER(0x0afc, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static struct peri_clk_data bsc2_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	.gate		= HW_SW_GATE(0x045c, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	.clocks		= CLOCKS("ref_crystal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 				 "var_104m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 				 "ref_104m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 				 "var_13m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 				 "ref_13m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	.sel		= SELECTOR(0x0a68, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.trig		= TRIGGER(0x0afc, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static struct peri_clk_data bsc3_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	.gate		= HW_SW_GATE(0x0470, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	.clocks		= CLOCKS("ref_crystal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 				 "var_104m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 				 "ref_104m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 				 "var_13m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 				 "ref_13m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	.sel		= SELECTOR(0x0a7c, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	.trig		= TRIGGER(0x0afc, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static struct peri_clk_data bsc4_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	.gate		= HW_SW_GATE(0x0474, 18, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	.clocks		= CLOCKS("ref_crystal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 				 "var_104m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 				 "ref_104m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 				 "var_13m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 				 "ref_13m"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	.sel		= SELECTOR(0x0a80, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	.trig		= TRIGGER(0x0afc, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static struct ccu_data slave_ccu_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	BCM21664_CCU_COMMON(slave, SLAVE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)        .policy		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		.enable		= CCU_LVM_EN(0x0034, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		.control	= CCU_POLICY_CTL(0x000c, 0, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.kona_clks	= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		[BCM21664_SLAVE_CCU_UARTB] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			KONA_CLK(slave, uartb, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		[BCM21664_SLAVE_CCU_UARTB2] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 			KONA_CLK(slave, uartb2, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		[BCM21664_SLAVE_CCU_UARTB3] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			KONA_CLK(slave, uartb3, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		[BCM21664_SLAVE_CCU_BSC1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 			KONA_CLK(slave, bsc1, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		[BCM21664_SLAVE_CCU_BSC2] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			KONA_CLK(slave, bsc2, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		[BCM21664_SLAVE_CCU_BSC3] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			KONA_CLK(slave, bsc3, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		[BCM21664_SLAVE_CCU_BSC4] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			KONA_CLK(slave, bsc4, peri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		[BCM21664_SLAVE_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* Device tree match table callback functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static void __init kona_dt_root_ccu_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	kona_dt_ccu_setup(&root_ccu_data, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static void __init kona_dt_aon_ccu_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	kona_dt_ccu_setup(&aon_ccu_data, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static void __init kona_dt_master_ccu_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	kona_dt_ccu_setup(&master_ccu_data, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static void __init kona_dt_slave_ccu_setup(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	kona_dt_ccu_setup(&slave_ccu_data, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) CLK_OF_DECLARE(bcm21664_root_ccu, BCM21664_DT_ROOT_CCU_COMPAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 			kona_dt_root_ccu_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) CLK_OF_DECLARE(bcm21664_aon_ccu, BCM21664_DT_AON_CCU_COMPAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 			kona_dt_aon_ccu_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) CLK_OF_DECLARE(bcm21664_master_ccu, BCM21664_DT_MASTER_CCU_COMPAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 			kona_dt_master_ccu_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) CLK_OF_DECLARE(bcm21664_slave_ccu, BCM21664_DT_SLAVE_CCU_COMPAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 			kona_dt_slave_ccu_setup);