^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Serge Semin <Sergey.Semin@baikalelectronics.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Dmitry Dunaev <dmitry.dunaev@baikalelectronics.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Baikal-T1 CCU PLL clocks driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define pr_fmt(fmt) "bt1-ccu-pll: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/printk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <dt-bindings/clock/bt1-ccu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "ccu-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CCU_CPU_PLL_BASE 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CCU_SATA_PLL_BASE 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CCU_DDR_PLL_BASE 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CCU_PCIE_PLL_BASE 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CCU_ETH_PLL_BASE 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CCU_PLL_INFO(_id, _name, _pname, _base, _flags) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .parent_name = _pname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .base = _base, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .flags = _flags \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CCU_PLL_NUM ARRAY_SIZE(pll_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct ccu_pll_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned int base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Alas we have to mark all PLLs as critical. CPU and DDR PLLs are sources of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * CPU cores and DDR controller reference clocks, due to which they obviously
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * shouldn't be ever gated. SATA and PCIe PLLs are the parents of APB-bus and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * DDR controller AXI-bus clocks. If they are gated the system will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * unusable. Moreover disabling SATA and Ethernet PLLs causes automatic reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * of the corresponding subsystems. So until we aren't ready to re-initialize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * all the devices consuming those PLLs, they will be marked as critical too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static const struct ccu_pll_info pll_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) CCU_PLL_INFO(CCU_CPU_PLL, "cpu_pll", "ref_clk", CCU_CPU_PLL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) CLK_IS_CRITICAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) CCU_PLL_INFO(CCU_SATA_PLL, "sata_pll", "ref_clk", CCU_SATA_PLL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) CLK_IS_CRITICAL | CLK_SET_RATE_GATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) CCU_PLL_INFO(CCU_DDR_PLL, "ddr_pll", "ref_clk", CCU_DDR_PLL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) CLK_IS_CRITICAL | CLK_SET_RATE_GATE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) CCU_PLL_INFO(CCU_PCIE_PLL, "pcie_pll", "ref_clk", CCU_PCIE_PLL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) CLK_IS_CRITICAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) CCU_PLL_INFO(CCU_ETH_PLL, "eth_pll", "ref_clk", CCU_ETH_PLL_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) CLK_IS_CRITICAL | CLK_SET_RATE_GATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct ccu_pll_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct regmap *sys_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct ccu_pll *plls[CCU_PLL_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static struct ccu_pll *ccu_pll_find_desc(struct ccu_pll_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned int clk_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct ccu_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) for (idx = 0; idx < CCU_PLL_NUM; ++idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) pll = data->plls[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (pll && pll->id == clk_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static struct ccu_pll_data *ccu_pll_create_data(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct ccu_pll_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) data = kzalloc(sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) data->np = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void ccu_pll_free_data(struct ccu_pll_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int ccu_pll_find_sys_regs(struct ccu_pll_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) data->sys_regs = syscon_node_to_regmap(data->np->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (IS_ERR(data->sys_regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) pr_err("Failed to find syscon regs for '%s'\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) of_node_full_name(data->np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return PTR_ERR(data->sys_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static struct clk_hw *ccu_pll_of_clk_hw_get(struct of_phandle_args *clkspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) void *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct ccu_pll_data *data = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct ccu_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned int clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) clk_id = clkspec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pll = ccu_pll_find_desc(data, clk_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (IS_ERR(pll)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) pr_info("Invalid PLL clock ID %d specified\n", clk_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return ERR_CAST(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return ccu_pll_get_clk_hw(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int ccu_pll_clk_register(struct ccu_pll_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int idx, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) for (idx = 0; idx < CCU_PLL_NUM; ++idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) const struct ccu_pll_info *info = &pll_info[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct ccu_pll_init_data init = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) init.id = info->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) init.name = info->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) init.parent_name = info->parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) init.base = info->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) init.sys_regs = data->sys_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) init.np = data->np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) init.flags = info->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) data->plls[idx] = ccu_pll_hw_register(&init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (IS_ERR(data->plls[idx])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ret = PTR_ERR(data->plls[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) pr_err("Couldn't register PLL hw '%s'\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) init.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) goto err_hw_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ret = of_clk_add_hw_provider(data->np, ccu_pll_of_clk_hw_get, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) pr_err("Couldn't register PLL provider of '%s'\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) of_node_full_name(data->np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) goto err_hw_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) err_hw_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) for (--idx; idx >= 0; --idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) ccu_pll_hw_unregister(data->plls[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static __init void ccu_pll_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct ccu_pll_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) data = ccu_pll_create_data(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (IS_ERR(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ret = ccu_pll_find_sys_regs(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) goto err_free_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ret = ccu_pll_clk_register(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) goto err_free_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) err_free_data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ccu_pll_free_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) CLK_OF_DECLARE(ccu_pll, "baikal,bt1-ccu-pll", ccu_pll_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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