^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Serge Semin <Sergey.Semin@baikalelectronics.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Dmitry Dunaev <dmitry.dunaev@baikalelectronics.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Baikal-T1 CCU Dividers clock driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define pr_fmt(fmt) "bt1-ccu-div: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/printk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/reset-controller.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <dt-bindings/clock/bt1-ccu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <dt-bindings/reset/bt1-ccu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "ccu-div.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CCU_AXI_MAIN_BASE 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CCU_AXI_DDR_BASE 0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CCU_AXI_SATA_BASE 0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CCU_AXI_GMAC0_BASE 0x03C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CCU_AXI_GMAC1_BASE 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CCU_AXI_XGMAC_BASE 0x044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CCU_AXI_PCIE_M_BASE 0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CCU_AXI_PCIE_S_BASE 0x04C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CCU_AXI_USB_BASE 0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CCU_AXI_HWA_BASE 0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CCU_AXI_SRAM_BASE 0x058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CCU_SYS_SATA_REF_BASE 0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CCU_SYS_APB_BASE 0x064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CCU_SYS_GMAC0_BASE 0x068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CCU_SYS_GMAC1_BASE 0x06C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CCU_SYS_XGMAC_BASE 0x070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CCU_SYS_USB_BASE 0x074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CCU_SYS_PVT_BASE 0x078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CCU_SYS_HWA_BASE 0x07C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CCU_SYS_UART_BASE 0x084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CCU_SYS_TIMER0_BASE 0x088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CCU_SYS_TIMER1_BASE 0x08C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CCU_SYS_TIMER2_BASE 0x090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CCU_SYS_WDT_BASE 0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CCU_DIV_VAR_INFO(_id, _name, _pname, _base, _width, _flags, _features) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .parent_name = _pname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .base = _base, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .type = CCU_DIV_VAR, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .width = _width, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .flags = _flags, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .features = _features \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CCU_DIV_GATE_INFO(_id, _name, _pname, _base, _divider) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .parent_name = _pname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .base = _base, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .type = CCU_DIV_GATE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .divider = _divider \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CCU_DIV_FIXED_INFO(_id, _name, _pname, _divider) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .parent_name = _pname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .type = CCU_DIV_FIXED, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .divider = _divider \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CCU_DIV_RST_MAP(_rst_id, _clk_id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .rst_id = _rst_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .clk_id = _clk_id \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct ccu_div_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) enum ccu_div_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned int width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned long features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct ccu_div_rst_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned int rst_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned int clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct ccu_div_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct regmap *sys_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned int divs_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) const struct ccu_div_info *divs_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct ccu_div **divs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned int rst_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) const struct ccu_div_rst_map *rst_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct reset_controller_dev rcdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define to_ccu_div_data(_rcdev) container_of(_rcdev, struct ccu_div_data, rcdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * AXI Main Interconnect (axi_main_clk) and DDR AXI-bus (axi_ddr_clk) clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * must be left enabled in any case, since former one is responsible for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * clocking a bus between CPU cores and the rest of the SoC components, while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * the later is clocking the AXI-bus between DDR controller and the Main
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * Interconnect. So should any of these clocks get to be disabled, the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * will literally stop working. That's why we marked them as critical.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static const struct ccu_div_info axi_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) CCU_DIV_VAR_INFO(CCU_AXI_MAIN_CLK, "axi_main_clk", "pcie_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) CCU_AXI_MAIN_BASE, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) CLK_IS_CRITICAL, CCU_DIV_RESET_DOMAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) CCU_DIV_VAR_INFO(CCU_AXI_DDR_CLK, "axi_ddr_clk", "sata_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) CCU_AXI_DDR_BASE, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) CCU_DIV_RESET_DOMAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) CCU_DIV_VAR_INFO(CCU_AXI_SATA_CLK, "axi_sata_clk", "sata_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) CCU_AXI_SATA_BASE, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) CCU_DIV_VAR_INFO(CCU_AXI_GMAC0_CLK, "axi_gmac0_clk", "eth_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) CCU_AXI_GMAC0_BASE, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) CCU_DIV_VAR_INFO(CCU_AXI_GMAC1_CLK, "axi_gmac1_clk", "eth_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) CCU_AXI_GMAC1_BASE, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) CCU_DIV_VAR_INFO(CCU_AXI_XGMAC_CLK, "axi_xgmac_clk", "eth_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) CCU_AXI_XGMAC_BASE, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) CCU_DIV_VAR_INFO(CCU_AXI_PCIE_M_CLK, "axi_pcie_m_clk", "pcie_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) CCU_AXI_PCIE_M_BASE, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) CCU_DIV_VAR_INFO(CCU_AXI_PCIE_S_CLK, "axi_pcie_s_clk", "pcie_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) CCU_AXI_PCIE_S_BASE, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) CCU_DIV_VAR_INFO(CCU_AXI_USB_CLK, "axi_usb_clk", "sata_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) CCU_AXI_USB_BASE, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) CCU_DIV_VAR_INFO(CCU_AXI_HWA_CLK, "axi_hwa_clk", "sata_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) CCU_AXI_HWA_BASE, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) CCU_DIV_VAR_INFO(CCU_AXI_SRAM_CLK, "axi_sram_clk", "eth_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) CCU_AXI_SRAM_BASE, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const struct ccu_div_rst_map axi_rst_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) CCU_DIV_RST_MAP(CCU_AXI_MAIN_RST, CCU_AXI_MAIN_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) CCU_DIV_RST_MAP(CCU_AXI_DDR_RST, CCU_AXI_DDR_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) CCU_DIV_RST_MAP(CCU_AXI_SATA_RST, CCU_AXI_SATA_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) CCU_DIV_RST_MAP(CCU_AXI_GMAC0_RST, CCU_AXI_GMAC0_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) CCU_DIV_RST_MAP(CCU_AXI_GMAC1_RST, CCU_AXI_GMAC1_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) CCU_DIV_RST_MAP(CCU_AXI_XGMAC_RST, CCU_AXI_XGMAC_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) CCU_DIV_RST_MAP(CCU_AXI_PCIE_M_RST, CCU_AXI_PCIE_M_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) CCU_DIV_RST_MAP(CCU_AXI_PCIE_S_RST, CCU_AXI_PCIE_S_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) CCU_DIV_RST_MAP(CCU_AXI_USB_RST, CCU_AXI_USB_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) CCU_DIV_RST_MAP(CCU_AXI_HWA_RST, CCU_AXI_HWA_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) CCU_DIV_RST_MAP(CCU_AXI_SRAM_RST, CCU_AXI_SRAM_CLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * APB-bus clock is marked as critical since it's a main communication bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * for the SoC devices registers IO-operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static const struct ccu_div_info sys_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) CCU_DIV_VAR_INFO(CCU_SYS_SATA_REF_CLK, "sys_sata_ref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "sata_clk", CCU_SYS_SATA_REF_BASE, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) CLK_SET_RATE_GATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) CCU_DIV_SKIP_ONE | CCU_DIV_LOCK_SHIFTED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) CCU_DIV_RESET_DOMAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) CCU_DIV_VAR_INFO(CCU_SYS_APB_CLK, "sys_apb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) "pcie_clk", CCU_SYS_APB_BASE, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) CLK_IS_CRITICAL, CCU_DIV_RESET_DOMAIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) CCU_DIV_GATE_INFO(CCU_SYS_GMAC0_TX_CLK, "sys_gmac0_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) "eth_clk", CCU_SYS_GMAC0_BASE, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) CCU_DIV_FIXED_INFO(CCU_SYS_GMAC0_PTP_CLK, "sys_gmac0_ptp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "eth_clk", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) CCU_DIV_GATE_INFO(CCU_SYS_GMAC1_TX_CLK, "sys_gmac1_tx_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "eth_clk", CCU_SYS_GMAC1_BASE, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) CCU_DIV_FIXED_INFO(CCU_SYS_GMAC1_PTP_CLK, "sys_gmac1_ptp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "eth_clk", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) CCU_DIV_GATE_INFO(CCU_SYS_XGMAC_REF_CLK, "sys_xgmac_ref_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "eth_clk", CCU_SYS_XGMAC_BASE, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) CCU_DIV_FIXED_INFO(CCU_SYS_XGMAC_PTP_CLK, "sys_xgmac_ptp_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) "eth_clk", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) CCU_DIV_GATE_INFO(CCU_SYS_USB_CLK, "sys_usb_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "eth_clk", CCU_SYS_USB_BASE, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) CCU_DIV_VAR_INFO(CCU_SYS_PVT_CLK, "sys_pvt_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) "ref_clk", CCU_SYS_PVT_BASE, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) CLK_SET_RATE_GATE, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) CCU_DIV_VAR_INFO(CCU_SYS_HWA_CLK, "sys_hwa_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) "sata_clk", CCU_SYS_HWA_BASE, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) CLK_SET_RATE_GATE, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) CCU_DIV_VAR_INFO(CCU_SYS_UART_CLK, "sys_uart_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) "eth_clk", CCU_SYS_UART_BASE, 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) CLK_SET_RATE_GATE, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) CCU_DIV_FIXED_INFO(CCU_SYS_I2C1_CLK, "sys_i2c1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) "eth_clk", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) CCU_DIV_FIXED_INFO(CCU_SYS_I2C2_CLK, "sys_i2c2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) "eth_clk", 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) CCU_DIV_FIXED_INFO(CCU_SYS_GPIO_CLK, "sys_gpio_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) "ref_clk", 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) CCU_DIV_VAR_INFO(CCU_SYS_TIMER0_CLK, "sys_timer0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) "ref_clk", CCU_SYS_TIMER0_BASE, 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) CLK_SET_RATE_GATE, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) CCU_DIV_VAR_INFO(CCU_SYS_TIMER1_CLK, "sys_timer1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) "ref_clk", CCU_SYS_TIMER1_BASE, 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) CLK_SET_RATE_GATE, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) CCU_DIV_VAR_INFO(CCU_SYS_TIMER2_CLK, "sys_timer2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) "ref_clk", CCU_SYS_TIMER2_BASE, 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) CLK_SET_RATE_GATE, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) CCU_DIV_VAR_INFO(CCU_SYS_WDT_CLK, "sys_wdt_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) "eth_clk", CCU_SYS_WDT_BASE, 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) CLK_SET_RATE_GATE, CCU_DIV_SKIP_ONE_TO_THREE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const struct ccu_div_rst_map sys_rst_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) CCU_DIV_RST_MAP(CCU_SYS_SATA_REF_RST, CCU_SYS_SATA_REF_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) CCU_DIV_RST_MAP(CCU_SYS_APB_RST, CCU_SYS_APB_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static struct ccu_div *ccu_div_find_desc(struct ccu_div_data *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unsigned int clk_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct ccu_div *div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) for (idx = 0; idx < data->divs_num; ++idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) div = data->divs[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (div && div->id == clk_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int ccu_div_reset(struct reset_controller_dev *rcdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned long rst_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct ccu_div_data *data = to_ccu_div_data(rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) const struct ccu_div_rst_map *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct ccu_div *div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int idx, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) for (idx = 0, map = data->rst_map; idx < data->rst_num; ++idx, ++map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (map->rst_id == rst_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (idx == data->rst_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) pr_err("Invalid reset ID %lu specified\n", rst_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) div = ccu_div_find_desc(data, map->clk_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (IS_ERR(div)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) pr_err("Invalid clock ID %d in mapping\n", map->clk_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return PTR_ERR(div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ret = ccu_div_reset_domain(div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) pr_err("Reset isn't supported by divider %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) clk_hw_get_name(ccu_div_get_clk_hw(div)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static const struct reset_control_ops ccu_div_rst_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .reset = ccu_div_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static struct ccu_div_data *ccu_div_create_data(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct ccu_div_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) data = kzalloc(sizeof(*data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) data->np = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (of_device_is_compatible(np, "baikal,bt1-ccu-axi")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) data->divs_num = ARRAY_SIZE(axi_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) data->divs_info = axi_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) data->rst_num = ARRAY_SIZE(axi_rst_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) data->rst_map = axi_rst_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) } else if (of_device_is_compatible(np, "baikal,bt1-ccu-sys")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) data->divs_num = ARRAY_SIZE(sys_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) data->divs_info = sys_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) data->rst_num = ARRAY_SIZE(sys_rst_map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) data->rst_map = sys_rst_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) pr_err("Incompatible DT node '%s' specified\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) of_node_full_name(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) goto err_kfree_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) data->divs = kcalloc(data->divs_num, sizeof(*data->divs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (!data->divs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) goto err_kfree_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) err_kfree_data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static void ccu_div_free_data(struct ccu_div_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) kfree(data->divs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int ccu_div_find_sys_regs(struct ccu_div_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) data->sys_regs = syscon_node_to_regmap(data->np->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (IS_ERR(data->sys_regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) pr_err("Failed to find syscon regs for '%s'\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) of_node_full_name(data->np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return PTR_ERR(data->sys_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static struct clk_hw *ccu_div_of_clk_hw_get(struct of_phandle_args *clkspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) void *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct ccu_div_data *data = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct ccu_div *div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unsigned int clk_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) clk_id = clkspec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) div = ccu_div_find_desc(data, clk_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (IS_ERR(div)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) pr_info("Invalid clock ID %d specified\n", clk_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return ERR_CAST(div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return ccu_div_get_clk_hw(div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static int ccu_div_clk_register(struct ccu_div_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int idx, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) for (idx = 0; idx < data->divs_num; ++idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) const struct ccu_div_info *info = &data->divs_info[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct ccu_div_init_data init = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) init.id = info->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) init.name = info->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) init.parent_name = info->parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) init.np = data->np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) init.type = info->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) init.flags = info->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) init.features = info->features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (init.type == CCU_DIV_VAR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) init.base = info->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) init.sys_regs = data->sys_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) init.width = info->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) } else if (init.type == CCU_DIV_GATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) init.base = info->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) init.sys_regs = data->sys_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) init.divider = info->divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) init.divider = info->divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) data->divs[idx] = ccu_div_hw_register(&init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (IS_ERR(data->divs[idx])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ret = PTR_ERR(data->divs[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) pr_err("Couldn't register divider '%s' hw\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) init.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) goto err_hw_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ret = of_clk_add_hw_provider(data->np, ccu_div_of_clk_hw_get, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) pr_err("Couldn't register dividers '%s' clock provider\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) of_node_full_name(data->np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) goto err_hw_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) err_hw_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) for (--idx; idx >= 0; --idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) ccu_div_hw_unregister(data->divs[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static void ccu_div_clk_unregister(struct ccu_div_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) of_clk_del_provider(data->np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) for (idx = 0; idx < data->divs_num; ++idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ccu_div_hw_unregister(data->divs[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static int ccu_div_rst_register(struct ccu_div_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) data->rcdev.ops = &ccu_div_rst_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) data->rcdev.of_node = data->np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) data->rcdev.nr_resets = data->rst_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ret = reset_controller_register(&data->rcdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) pr_err("Couldn't register divider '%s' reset controller\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) of_node_full_name(data->np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static void ccu_div_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct ccu_div_data *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) data = ccu_div_create_data(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (IS_ERR(data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ret = ccu_div_find_sys_regs(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) goto err_free_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ret = ccu_div_clk_register(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) goto err_free_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ret = ccu_div_rst_register(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) goto err_clk_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) err_clk_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ccu_div_clk_unregister(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) err_free_data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ccu_div_free_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) CLK_OF_DECLARE(ccu_axi, "baikal,bt1-ccu-axi", ccu_div_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) CLK_OF_DECLARE(ccu_sys, "baikal,bt1-ccu-sys", ccu_div_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags