Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Baikal-T1 CCU PLL interface driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef __CLK_BT1_CCU_PLL_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define __CLK_BT1_CCU_PLL_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * struct ccu_pll_init_data - CCU PLL initialization data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  * @id: Clock private identifier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  * @name: Clocks name.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  * @parent_name: Clocks parent name in a fw node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  * @base: PLL registers base address with respect to the sys_regs base.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  * @sys_regs: Baikal-T1 System Controller registers map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  * @np: Pointer to the node describing the CCU PLLs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  * @flags: PLL clock flags.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct ccu_pll_init_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	unsigned int base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	struct regmap *sys_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)  * struct ccu_pll - CCU PLL descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)  * @hw: clk_hw of the PLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)  * @id: Clock private identifier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)  * @reg_ctl: PLL control register base.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)  * @reg_ctl1: PLL control1 register base.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)  * @sys_regs: Baikal-T1 System Controller registers map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)  * @lock: PLL state change spin-lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct ccu_pll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	unsigned int reg_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	unsigned int reg_ctl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	struct regmap *sys_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define to_ccu_pll(_hw) container_of(_hw, struct ccu_pll, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static inline struct clk_hw *ccu_pll_get_clk_hw(struct ccu_pll *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	return pll ? &pll->hw : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct ccu_pll *ccu_pll_hw_register(const struct ccu_pll_init_data *init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) void ccu_pll_hw_unregister(struct ccu_pll *pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #endif /* __CLK_BT1_CCU_PLL_H__ */