^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Authors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Serge Semin <Sergey.Semin@baikalelectronics.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Dmitry Dunaev <dmitry.dunaev@baikalelectronics.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Baikal-T1 CCU PLL interface driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define pr_fmt(fmt) "bt1-ccu-pll: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/printk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/limits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/bits.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/time64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/rational.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "ccu-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CCU_PLL_CTL 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CCU_PLL_CTL_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CCU_PLL_CTL_RST BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CCU_PLL_CTL_CLKR_FLD 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CCU_PLL_CTL_CLKR_MASK GENMASK(7, CCU_PLL_CTL_CLKR_FLD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CCU_PLL_CTL_CLKF_FLD 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CCU_PLL_CTL_CLKF_MASK GENMASK(20, CCU_PLL_CTL_CLKF_FLD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CCU_PLL_CTL_CLKOD_FLD 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CCU_PLL_CTL_CLKOD_MASK GENMASK(24, CCU_PLL_CTL_CLKOD_FLD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CCU_PLL_CTL_BYPASS BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CCU_PLL_CTL_LOCK BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CCU_PLL_CTL1 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CCU_PLL_CTL1_BWADJ_FLD 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CCU_PLL_CTL1_BWADJ_MASK GENMASK(14, CCU_PLL_CTL1_BWADJ_FLD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CCU_PLL_LOCK_CHECK_RETRIES 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CCU_PLL_NR_MAX \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ((CCU_PLL_CTL_CLKR_MASK >> CCU_PLL_CTL_CLKR_FLD) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CCU_PLL_NF_MAX \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ((CCU_PLL_CTL_CLKF_MASK >> (CCU_PLL_CTL_CLKF_FLD + 1)) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CCU_PLL_OD_MAX \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ((CCU_PLL_CTL_CLKOD_MASK >> CCU_PLL_CTL_CLKOD_FLD) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CCU_PLL_NB_MAX \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ((CCU_PLL_CTL1_BWADJ_MASK >> CCU_PLL_CTL1_BWADJ_FLD) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CCU_PLL_FDIV_MIN 427000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CCU_PLL_FDIV_MAX 3500000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CCU_PLL_FOUT_MIN 200000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CCU_PLL_FOUT_MAX 2500000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CCU_PLL_FVCO_MIN 700000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CCU_PLL_FVCO_MAX 3500000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CCU_PLL_CLKOD_FACTOR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static inline unsigned long ccu_pll_lock_delay_us(unsigned long ref_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) unsigned long nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u64 us = 500ULL * nr * USEC_PER_SEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) do_div(us, ref_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static inline unsigned long ccu_pll_calc_freq(unsigned long ref_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned long nr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned long nf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned long od)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u64 tmp = ref_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) do_div(tmp, nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) tmp *= nf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) do_div(tmp, od);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int ccu_pll_reset(struct ccu_pll *pll, unsigned long ref_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned long nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned long ud, ut;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ud = ccu_pll_lock_delay_us(ref_clk, nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ut = ud * CCU_PLL_LOCK_CHECK_RETRIES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) regmap_update_bits(pll->sys_regs, pll->reg_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) CCU_PLL_CTL_RST, CCU_PLL_CTL_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return regmap_read_poll_timeout_atomic(pll->sys_regs, pll->reg_ctl, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) val & CCU_PLL_CTL_LOCK, ud, ut);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int ccu_pll_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct clk_hw *parent_hw = clk_hw_get_parent(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct ccu_pll *pll = to_ccu_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (!parent_hw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pr_err("Can't enable '%s' with no parent", clk_hw_get_name(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) regmap_read(pll->sys_regs, pll->reg_ctl, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (val & CCU_PLL_CTL_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) spin_lock_irqsave(&pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) regmap_write(pll->sys_regs, pll->reg_ctl, val | CCU_PLL_CTL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ret = ccu_pll_reset(pll, clk_hw_get_rate(parent_hw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) FIELD_GET(CCU_PLL_CTL_CLKR_MASK, val) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) spin_unlock_irqrestore(&pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) pr_err("PLL '%s' reset timed out\n", clk_hw_get_name(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static void ccu_pll_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct ccu_pll *pll = to_ccu_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) spin_lock_irqsave(&pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) regmap_update_bits(pll->sys_regs, pll->reg_ctl, CCU_PLL_CTL_EN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) spin_unlock_irqrestore(&pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int ccu_pll_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct ccu_pll *pll = to_ccu_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) regmap_read(pll->sys_regs, pll->reg_ctl, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return !!(val & CCU_PLL_CTL_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static unsigned long ccu_pll_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct ccu_pll *pll = to_ccu_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned long nr, nf, od;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) regmap_read(pll->sys_regs, pll->reg_ctl, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) nr = FIELD_GET(CCU_PLL_CTL_CLKR_MASK, val) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) nf = FIELD_GET(CCU_PLL_CTL_CLKF_MASK, val) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) od = FIELD_GET(CCU_PLL_CTL_CLKOD_MASK, val) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return ccu_pll_calc_freq(parent_rate, nr, nf, od);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static void ccu_pll_calc_factors(unsigned long rate, unsigned long parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned long *nr, unsigned long *nf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned long *od)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned long err, freq, min_err = ULONG_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned long num, denom, n1, d1, nri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned long nr_max, nf_max, od_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * Make sure PLL is working with valid input signal (Fdiv). If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * you want to speed the function up just reduce CCU_PLL_NR_MAX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * This will cause a worse approximation though.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) nri = (parent_rate / CCU_PLL_FDIV_MAX) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) nr_max = min(parent_rate / CCU_PLL_FDIV_MIN, CCU_PLL_NR_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * Find a closest [nr;nf;od] vector taking into account the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * limitations like: 1) 700MHz <= Fvco <= 3.5GHz, 2) PLL Od is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * either 1 or even number within the acceptable range (alas 1s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * is also excluded by the next loop).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) for (; nri <= nr_max; ++nri) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Use Od factor to fulfill the limitation 2). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) num = CCU_PLL_CLKOD_FACTOR * rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) denom = parent_rate / nri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * Make sure Fvco is within the acceptable range to fulfill
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * the condition 1). Note due to the CCU_PLL_CLKOD_FACTOR value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * the actual upper limit is also divided by that factor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * It's not big problem for us since practically there is no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * need in clocks with that high frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) nf_max = min(CCU_PLL_FVCO_MAX / denom, CCU_PLL_NF_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) od_max = CCU_PLL_OD_MAX / CCU_PLL_CLKOD_FACTOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * Bypass the out-of-bound values, which can't be properly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * handled by the rational fraction approximation algorithm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (num / denom >= nf_max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) n1 = nf_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) d1 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) } else if (denom / num >= od_max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) n1 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) d1 = od_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) rational_best_approximation(num, denom, nf_max, od_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) &n1, &d1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* Select the best approximation of the target rate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) freq = ccu_pll_calc_freq(parent_rate, nri, n1, d1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) err = abs((int64_t)freq - num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (err < min_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) min_err = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) *nr = nri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) *nf = n1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *od = CCU_PLL_CLKOD_FACTOR * d1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static long ccu_pll_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned long nr = 1, nf = 1, od = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ccu_pll_calc_factors(rate, *parent_rate, &nr, &nf, &od);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return ccu_pll_calc_freq(*parent_rate, nr, nf, od);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * This method is used for PLLs, which support the on-the-fly dividers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * adjustment. So there is no need in gating such clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int ccu_pll_set_rate_reset(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct ccu_pll *pll = to_ccu_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned long nr, nf, od;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u32 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ccu_pll_calc_factors(rate, parent_rate, &nr, &nf, &od);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) mask = CCU_PLL_CTL_CLKR_MASK | CCU_PLL_CTL_CLKF_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) CCU_PLL_CTL_CLKOD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) val = FIELD_PREP(CCU_PLL_CTL_CLKR_MASK, nr - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) FIELD_PREP(CCU_PLL_CTL_CLKF_MASK, nf - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) FIELD_PREP(CCU_PLL_CTL_CLKOD_MASK, od - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) spin_lock_irqsave(&pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) regmap_update_bits(pll->sys_regs, pll->reg_ctl, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ret = ccu_pll_reset(pll, parent_rate, nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) spin_unlock_irqrestore(&pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) pr_err("PLL '%s' reset timed out\n", clk_hw_get_name(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * This method is used for PLLs, which don't support the on-the-fly dividers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * adjustment. So the corresponding clocks are supposed to be gated first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int ccu_pll_set_rate_norst(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct ccu_pll *pll = to_ccu_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned long nr, nf, od;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u32 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ccu_pll_calc_factors(rate, parent_rate, &nr, &nf, &od);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * Disable PLL if it was enabled by default or left enabled by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * system bootloader.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) mask = CCU_PLL_CTL_CLKR_MASK | CCU_PLL_CTL_CLKF_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) CCU_PLL_CTL_CLKOD_MASK | CCU_PLL_CTL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) val = FIELD_PREP(CCU_PLL_CTL_CLKR_MASK, nr - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) FIELD_PREP(CCU_PLL_CTL_CLKF_MASK, nf - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) FIELD_PREP(CCU_PLL_CTL_CLKOD_MASK, od - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) spin_lock_irqsave(&pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) regmap_update_bits(pll->sys_regs, pll->reg_ctl, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) spin_unlock_irqrestore(&pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct ccu_pll_dbgfs_bit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct ccu_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct ccu_pll_dbgfs_fld {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct ccu_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) unsigned int lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u32 min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u32 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define CCU_PLL_DBGFS_BIT_ATTR(_name, _reg, _mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .mask = _mask \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define CCU_PLL_DBGFS_FLD_ATTR(_name, _reg, _lsb, _mask, _min, _max) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .lsb = _lsb, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .mask = _mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .min = _min, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .max = _max \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static const struct ccu_pll_dbgfs_bit ccu_pll_bits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) CCU_PLL_DBGFS_BIT_ATTR("pll_en", CCU_PLL_CTL, CCU_PLL_CTL_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) CCU_PLL_DBGFS_BIT_ATTR("pll_rst", CCU_PLL_CTL, CCU_PLL_CTL_RST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) CCU_PLL_DBGFS_BIT_ATTR("pll_bypass", CCU_PLL_CTL, CCU_PLL_CTL_BYPASS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) CCU_PLL_DBGFS_BIT_ATTR("pll_lock", CCU_PLL_CTL, CCU_PLL_CTL_LOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define CCU_PLL_DBGFS_BIT_NUM ARRAY_SIZE(ccu_pll_bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const struct ccu_pll_dbgfs_fld ccu_pll_flds[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) CCU_PLL_DBGFS_FLD_ATTR("pll_nr", CCU_PLL_CTL, CCU_PLL_CTL_CLKR_FLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) CCU_PLL_CTL_CLKR_MASK, 1, CCU_PLL_NR_MAX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) CCU_PLL_DBGFS_FLD_ATTR("pll_nf", CCU_PLL_CTL, CCU_PLL_CTL_CLKF_FLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) CCU_PLL_CTL_CLKF_MASK, 1, CCU_PLL_NF_MAX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) CCU_PLL_DBGFS_FLD_ATTR("pll_od", CCU_PLL_CTL, CCU_PLL_CTL_CLKOD_FLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) CCU_PLL_CTL_CLKOD_MASK, 1, CCU_PLL_OD_MAX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) CCU_PLL_DBGFS_FLD_ATTR("pll_nb", CCU_PLL_CTL1, CCU_PLL_CTL1_BWADJ_FLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) CCU_PLL_CTL1_BWADJ_MASK, 1, CCU_PLL_NB_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define CCU_PLL_DBGFS_FLD_NUM ARRAY_SIZE(ccu_pll_flds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * It can be dangerous to change the PLL settings behind clock framework back,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * therefore we don't provide any kernel config based compile time option for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * this feature to enable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #undef CCU_PLL_ALLOW_WRITE_DEBUGFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #ifdef CCU_PLL_ALLOW_WRITE_DEBUGFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static int ccu_pll_dbgfs_bit_set(void *priv, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) const struct ccu_pll_dbgfs_bit *bit = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct ccu_pll *pll = bit->pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) spin_lock_irqsave(&pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) regmap_update_bits(pll->sys_regs, pll->reg_ctl + bit->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) bit->mask, val ? bit->mask : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) spin_unlock_irqrestore(&pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int ccu_pll_dbgfs_fld_set(void *priv, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct ccu_pll_dbgfs_fld *fld = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct ccu_pll *pll = fld->pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) val = clamp_t(u64, val, fld->min, fld->max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) data = ((val - 1) << fld->lsb) & fld->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) spin_lock_irqsave(&pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) regmap_update_bits(pll->sys_regs, pll->reg_ctl + fld->reg, fld->mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) spin_unlock_irqrestore(&pll->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define ccu_pll_dbgfs_mode 0644
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #else /* !CCU_PLL_ALLOW_WRITE_DEBUGFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define ccu_pll_dbgfs_bit_set NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define ccu_pll_dbgfs_fld_set NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define ccu_pll_dbgfs_mode 0444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #endif /* !CCU_PLL_ALLOW_WRITE_DEBUGFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static int ccu_pll_dbgfs_bit_get(void *priv, u64 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) struct ccu_pll_dbgfs_bit *bit = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) struct ccu_pll *pll = bit->pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) regmap_read(pll->sys_regs, pll->reg_ctl + bit->reg, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) *val = !!(data & bit->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) DEFINE_DEBUGFS_ATTRIBUTE(ccu_pll_dbgfs_bit_fops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) ccu_pll_dbgfs_bit_get, ccu_pll_dbgfs_bit_set, "%llu\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static int ccu_pll_dbgfs_fld_get(void *priv, u64 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct ccu_pll_dbgfs_fld *fld = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct ccu_pll *pll = fld->pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) u32 data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) regmap_read(pll->sys_regs, pll->reg_ctl + fld->reg, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) *val = ((data & fld->mask) >> fld->lsb) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) DEFINE_DEBUGFS_ATTRIBUTE(ccu_pll_dbgfs_fld_fops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ccu_pll_dbgfs_fld_get, ccu_pll_dbgfs_fld_set, "%llu\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static void ccu_pll_debug_init(struct clk_hw *hw, struct dentry *dentry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct ccu_pll *pll = to_ccu_pll(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct ccu_pll_dbgfs_bit *bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct ccu_pll_dbgfs_fld *flds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) bits = kcalloc(CCU_PLL_DBGFS_BIT_NUM, sizeof(*bits), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (!bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) for (idx = 0; idx < CCU_PLL_DBGFS_BIT_NUM; ++idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) bits[idx] = ccu_pll_bits[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) bits[idx].pll = pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) debugfs_create_file_unsafe(bits[idx].name, ccu_pll_dbgfs_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) dentry, &bits[idx],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) &ccu_pll_dbgfs_bit_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) flds = kcalloc(CCU_PLL_DBGFS_FLD_NUM, sizeof(*flds), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (!flds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) for (idx = 0; idx < CCU_PLL_DBGFS_FLD_NUM; ++idx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) flds[idx] = ccu_pll_flds[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) flds[idx].pll = pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) debugfs_create_file_unsafe(flds[idx].name, ccu_pll_dbgfs_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) dentry, &flds[idx],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) &ccu_pll_dbgfs_fld_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #else /* !CONFIG_DEBUG_FS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define ccu_pll_debug_init NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #endif /* !CONFIG_DEBUG_FS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static const struct clk_ops ccu_pll_gate_to_set_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .enable = ccu_pll_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .disable = ccu_pll_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .is_enabled = ccu_pll_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .recalc_rate = ccu_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .round_rate = ccu_pll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .set_rate = ccu_pll_set_rate_norst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .debug_init = ccu_pll_debug_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static const struct clk_ops ccu_pll_straight_set_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .enable = ccu_pll_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .disable = ccu_pll_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .is_enabled = ccu_pll_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .recalc_rate = ccu_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .round_rate = ccu_pll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .set_rate = ccu_pll_set_rate_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .debug_init = ccu_pll_debug_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct ccu_pll *ccu_pll_hw_register(const struct ccu_pll_init_data *pll_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct clk_parent_data parent_data = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct clk_init_data hw_init = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct ccu_pll *pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (!pll_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) pll = kzalloc(sizeof(*pll), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (!pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * Note since Baikal-T1 System Controller registers are MMIO-backed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * we won't check the regmap IO operations return status, because it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * must be zero anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) pll->hw.init = &hw_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) pll->reg_ctl = pll_init->base + CCU_PLL_CTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) pll->reg_ctl1 = pll_init->base + CCU_PLL_CTL1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) pll->sys_regs = pll_init->sys_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) pll->id = pll_init->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) spin_lock_init(&pll->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) hw_init.name = pll_init->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) hw_init.flags = pll_init->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (hw_init.flags & CLK_SET_RATE_GATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) hw_init.ops = &ccu_pll_gate_to_set_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) hw_init.ops = &ccu_pll_straight_set_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (!pll_init->parent_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) goto err_free_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) parent_data.fw_name = pll_init->parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) hw_init.parent_data = &parent_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) hw_init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ret = of_clk_hw_register(pll_init->np, &pll->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) goto err_free_pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return pll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) err_free_pll:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) void ccu_pll_hw_unregister(struct ccu_pll *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) clk_hw_unregister(&pll->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) kfree(pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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