Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) # SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) config CLK_BAIKAL_T1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 	bool "Baikal-T1 Clocks Control Unit interface"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 	depends on (MIPS_BAIKAL_T1 && OF) || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 	default MIPS_BAIKAL_T1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 	  Clocks Control Unit is the core of Baikal-T1 SoC System Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 	  responsible for the chip subsystems clocking and resetting. It
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 	  consists of multiple global clock domains, which can be reset by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	  means of the CCU control registers. These domains and devices placed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	  in them are fed with clocks generated by a hierarchy of PLLs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	  configurable and fixed clock dividers. Enable this option to be able
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	  to select Baikal-T1 CCU PLLs and Dividers drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) if CLK_BAIKAL_T1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) config CLK_BT1_CCU_PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	bool "Baikal-T1 CCU PLLs support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	select MFD_SYSCON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	default MIPS_BAIKAL_T1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	  Enable this to support the PLLs embedded into the Baikal-T1 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	  System Controller. These are five PLLs placed at the root of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	  clocks hierarchy, right after an external reference oscillator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	  (normally of 25MHz). They are used to generate high frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	  signals, which are either directly wired to the consumers (like
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	  CPUs, DDR, etc.) or passed over the clock dividers to be only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	  then used as an individual reference clock of a target device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) config CLK_BT1_CCU_DIV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	bool "Baikal-T1 CCU Dividers support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	select RESET_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	select MFD_SYSCON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	default MIPS_BAIKAL_T1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	  Enable this to support the CCU dividers used to distribute clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	  between AXI-bus and system devices coming from CCU PLLs of Baikal-T1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	  SoC. CCU dividers can be either configurable or with fixed divider,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	  either gateable or ungateable. Some of the CCU dividers can be as well
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	  used to reset the domains they're supplying clock to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) endif