^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ARTPEC-6 clock initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2015-2016 Axis Comunications AB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define NUM_I2S_CLOCKS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct artpec6_clkctrl_drvdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct clk *clk_table[ARTPEC6_CLK_NUMCLOCKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) void __iomem *syscon_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct clk_onecell_data clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) spinlock_t i2scfg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static struct artpec6_clkctrl_drvdata *clkdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static const char *const i2s_clk_names[NUM_I2S_CLOCKS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) "i2s0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) "i2s1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static const int i2s_clk_indexes[NUM_I2S_CLOCKS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) ARTPEC6_CLK_I2S0_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ARTPEC6_CLK_I2S1_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static void of_artpec6_clkctrl_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) const char *sys_refclk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 pll_mode, pll_m, pll_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct clk **clks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Mandatory parent clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) i = of_property_match_string(np, "clock-names", "sys_refclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) sys_refclk_name = of_clk_get_parent_name(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) clkdata = kzalloc(sizeof(*clkdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (!clkdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) clks = clkdata->clk_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) for (i = 0; i < ARTPEC6_CLK_NUMCLOCKS; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) clks[i] = ERR_PTR(-EPROBE_DEFER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) clkdata->syscon_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) BUG_ON(clkdata->syscon_base == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Read PLL1 factors configured by boot strap pins. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) pll_mode = (readl(clkdata->syscon_base) >> 6) & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) switch (pll_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) case 0: /* DDR3-2133 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) pll_m = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) pll_n = 85;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) case 1: /* DDR3-1866 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) pll_m = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) pll_n = 112;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) case 2: /* DDR3-1600 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) pll_m = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pll_n = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) case 3: /* DDR3-1333 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) pll_m = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) pll_n = 106;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) clks[ARTPEC6_CLK_CPU] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) clk_register_fixed_factor(NULL, "cpu", sys_refclk_name, 0, pll_n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) pll_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) clks[ARTPEC6_CLK_CPU_PERIPH] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) clk_register_fixed_factor(NULL, "cpu_periph", "cpu", 0, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* EPROBE_DEFER on the apb_clock is not handled in amba devices. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) clks[ARTPEC6_CLK_UART_PCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) clk_register_fixed_factor(NULL, "uart_pclk", "cpu", 0, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) clks[ARTPEC6_CLK_UART_REFCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) clk_register_fixed_rate(NULL, "uart_ref", sys_refclk_name, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 50000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) clks[ARTPEC6_CLK_SPI_PCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) clk_register_fixed_factor(NULL, "spi_pclk", "cpu", 0, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) clks[ARTPEC6_CLK_SPI_SSPCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) clk_register_fixed_rate(NULL, "spi_sspclk", sys_refclk_name, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 50000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) clks[ARTPEC6_CLK_DBG_PCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) clk_register_fixed_factor(NULL, "dbg_pclk", "cpu", 0, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) clkdata->clk_data.clks = clkdata->clk_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) clkdata->clk_data.clk_num = ARTPEC6_CLK_NUMCLOCKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) of_clk_add_provider(np, of_clk_src_onecell_get, &clkdata->clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) CLK_OF_DECLARE_DRIVER(artpec6_clkctrl, "axis,artpec6-clkctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) of_artpec6_clkctrl_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int artpec6_clkctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int propidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct clk **clks = clkdata->clk_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) const char *sys_refclk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) const char *i2s_refclk_name = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) const char *frac_clk_name[2] = { NULL, NULL };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) const char *i2s_mux_parents[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 muxreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Mandatory parent clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) propidx = of_property_match_string(np, "clock-names", "sys_refclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (propidx < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) sys_refclk_name = of_clk_get_parent_name(np, propidx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Find clock names of optional parent clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) propidx = of_property_match_string(np, "clock-names", "i2s_refclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (propidx >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) i2s_refclk_name = of_clk_get_parent_name(np, propidx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) propidx = of_property_match_string(np, "clock-names", "frac_clk0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (propidx >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) frac_clk_name[0] = of_clk_get_parent_name(np, propidx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) propidx = of_property_match_string(np, "clock-names", "frac_clk1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (propidx >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) frac_clk_name[1] = of_clk_get_parent_name(np, propidx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) spin_lock_init(&clkdata->i2scfg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) clks[ARTPEC6_CLK_NAND_CLKA] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) clk_register_fixed_factor(dev, "nand_clka", "cpu", 0, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) clks[ARTPEC6_CLK_NAND_CLKB] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) clk_register_fixed_rate(dev, "nand_clkb", sys_refclk_name, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 100000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) clks[ARTPEC6_CLK_ETH_ACLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) clk_register_fixed_factor(dev, "eth_aclk", "cpu", 0, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) clks[ARTPEC6_CLK_DMA_ACLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) clk_register_fixed_factor(dev, "dma_aclk", "cpu", 0, 1, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) clks[ARTPEC6_CLK_PTP_REF] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) clk_register_fixed_rate(dev, "ptp_ref", sys_refclk_name, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 100000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) clks[ARTPEC6_CLK_SD_PCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) clk_register_fixed_rate(dev, "sd_pclk", sys_refclk_name, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 100000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) clks[ARTPEC6_CLK_SD_IMCLK] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) clk_register_fixed_rate(dev, "sd_imclk", sys_refclk_name, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 100000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) clks[ARTPEC6_CLK_I2S_HST] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) clk_register_fixed_factor(dev, "i2s_hst", "cpu", 0, 1, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) for (i = 0; i < NUM_I2S_CLOCKS; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (i2s_refclk_name && frac_clk_name[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) i2s_mux_parents[0] = frac_clk_name[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) i2s_mux_parents[1] = i2s_refclk_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) clks[i2s_clk_indexes[i]] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) clk_register_mux(dev, i2s_clk_names[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) i2s_mux_parents, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) CLK_SET_RATE_NO_REPARENT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) CLK_SET_RATE_PARENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) clkdata->syscon_base + 0x14, i, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 0, &clkdata->i2scfg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) } else if (frac_clk_name[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Lock the mux for internal clock reference. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) muxreg = readl(clkdata->syscon_base + 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) muxreg &= ~BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) writel(muxreg, clkdata->syscon_base + 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) clks[i2s_clk_indexes[i]] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) clk_register_fixed_factor(dev, i2s_clk_names[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) frac_clk_name[i], 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) } else if (i2s_refclk_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* Lock the mux for external clock reference. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) muxreg = readl(clkdata->syscon_base + 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) muxreg |= BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) writel(muxreg, clkdata->syscon_base + 0x14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) clks[i2s_clk_indexes[i]] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) clk_register_fixed_factor(dev, i2s_clk_names[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) i2s_refclk_name, 0, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) clks[ARTPEC6_CLK_I2C] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) clk_register_fixed_rate(dev, "i2c", sys_refclk_name, 0, 100000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) clks[ARTPEC6_CLK_SYS_TIMER] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) clk_register_fixed_rate(dev, "timer", sys_refclk_name, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 100000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) clks[ARTPEC6_CLK_FRACDIV_IN] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) clk_register_fixed_rate(dev, "fracdiv_in", sys_refclk_name, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 600000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) for (i = 0; i < ARTPEC6_CLK_NUMCLOCKS; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (IS_ERR(clks[i]) && PTR_ERR(clks[i]) != -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) "Failed to register clock at index %d err=%ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) i, PTR_ERR(clks[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) err = PTR_ERR(clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const struct of_device_id artpec_clkctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { .compatible = "axis,artpec6-clkctrl" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static struct platform_driver artpec6_clkctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .probe = artpec6_clkctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .name = "artpec6_clkctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .of_match_table = artpec_clkctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) builtin_platform_driver(artpec6_clkctrl_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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