^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/clk/at91/sckc.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SLOW_CLOCK_FREQ 32768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SLOWCK_SW_CYCLES 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SLOWCK_SW_TIME_USEC ((SLOWCK_SW_CYCLES * USEC_PER_SEC) / \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) SLOW_CLOCK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define AT91_SCKC_CR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct clk_slow_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u32 cr_rcen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u32 cr_osc32en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u32 cr_osc32byp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u32 cr_oscsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct clk_slow_osc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) void __iomem *sckcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) const struct clk_slow_bits *bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned long startup_usec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define to_clk_slow_osc(hw) container_of(hw, struct clk_slow_osc, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct clk_sama5d4_slow_osc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) void __iomem *sckcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) const struct clk_slow_bits *bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned long startup_usec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) bool prepared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define to_clk_sama5d4_slow_osc(hw) container_of(hw, struct clk_sama5d4_slow_osc, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct clk_slow_rc_osc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) void __iomem *sckcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) const struct clk_slow_bits *bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned long frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned long accuracy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned long startup_usec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define to_clk_slow_rc_osc(hw) container_of(hw, struct clk_slow_rc_osc, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct clk_sam9x5_slow {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) void __iomem *sckcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) const struct clk_slow_bits *bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u8 parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define to_clk_sam9x5_slow(hw) container_of(hw, struct clk_sam9x5_slow, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int clk_slow_osc_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct clk_slow_osc *osc = to_clk_slow_osc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) void __iomem *sckcr = osc->sckcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 tmp = readl(sckcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (tmp & (osc->bits->cr_osc32byp | osc->bits->cr_osc32en))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) writel(tmp | osc->bits->cr_osc32en, sckcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (system_state < SYSTEM_RUNNING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) udelay(osc->startup_usec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) usleep_range(osc->startup_usec, osc->startup_usec + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) static void clk_slow_osc_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct clk_slow_osc *osc = to_clk_slow_osc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) void __iomem *sckcr = osc->sckcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 tmp = readl(sckcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (tmp & osc->bits->cr_osc32byp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) writel(tmp & ~osc->bits->cr_osc32en, sckcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int clk_slow_osc_is_prepared(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct clk_slow_osc *osc = to_clk_slow_osc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) void __iomem *sckcr = osc->sckcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 tmp = readl(sckcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (tmp & osc->bits->cr_osc32byp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return !!(tmp & osc->bits->cr_osc32en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const struct clk_ops slow_osc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .prepare = clk_slow_osc_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .unprepare = clk_slow_osc_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .is_prepared = clk_slow_osc_is_prepared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) at91_clk_register_slow_osc(void __iomem *sckcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned long startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) bool bypass,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) const struct clk_slow_bits *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct clk_slow_osc *osc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (!sckcr || !name || !parent_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) osc = kzalloc(sizeof(*osc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (!osc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) init.ops = &slow_osc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) init.flags = CLK_IGNORE_UNUSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) osc->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) osc->sckcr = sckcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) osc->startup_usec = startup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) osc->bits = bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (bypass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) writel((readl(sckcr) & ~osc->bits->cr_osc32en) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) osc->bits->cr_osc32byp, sckcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) hw = &osc->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ret = clk_hw_register(NULL, &osc->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) kfree(osc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static void at91_clk_unregister_slow_osc(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct clk_slow_osc *osc = to_clk_slow_osc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) clk_hw_unregister(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) kfree(osc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static unsigned long clk_slow_rc_osc_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return osc->frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static unsigned long clk_slow_rc_osc_recalc_accuracy(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned long parent_acc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return osc->accuracy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int clk_slow_rc_osc_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) void __iomem *sckcr = osc->sckcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) writel(readl(sckcr) | osc->bits->cr_rcen, sckcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (system_state < SYSTEM_RUNNING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) udelay(osc->startup_usec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) usleep_range(osc->startup_usec, osc->startup_usec + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static void clk_slow_rc_osc_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) void __iomem *sckcr = osc->sckcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) writel(readl(sckcr) & ~osc->bits->cr_rcen, sckcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int clk_slow_rc_osc_is_prepared(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return !!(readl(osc->sckcr) & osc->bits->cr_rcen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const struct clk_ops slow_rc_osc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .prepare = clk_slow_rc_osc_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .unprepare = clk_slow_rc_osc_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .is_prepared = clk_slow_rc_osc_is_prepared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .recalc_rate = clk_slow_rc_osc_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .recalc_accuracy = clk_slow_rc_osc_recalc_accuracy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) at91_clk_register_slow_rc_osc(void __iomem *sckcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned long frequency,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned long accuracy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned long startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) const struct clk_slow_bits *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct clk_slow_rc_osc *osc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (!sckcr || !name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) osc = kzalloc(sizeof(*osc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (!osc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) init.ops = &slow_rc_osc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) init.parent_names = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) init.num_parents = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) init.flags = CLK_IGNORE_UNUSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) osc->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) osc->sckcr = sckcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) osc->bits = bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) osc->frequency = frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) osc->accuracy = accuracy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) osc->startup_usec = startup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) hw = &osc->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ret = clk_hw_register(NULL, &osc->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) kfree(osc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static void at91_clk_unregister_slow_rc_osc(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) clk_hw_unregister(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) kfree(osc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int clk_sam9x5_slow_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) void __iomem *sckcr = slowck->sckcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (index > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) tmp = readl(sckcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if ((!index && !(tmp & slowck->bits->cr_oscsel)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) (index && (tmp & slowck->bits->cr_oscsel)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) tmp |= slowck->bits->cr_oscsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) tmp &= ~slowck->bits->cr_oscsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) writel(tmp, sckcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (system_state < SYSTEM_RUNNING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) udelay(SLOWCK_SW_TIME_USEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) usleep_range(SLOWCK_SW_TIME_USEC, SLOWCK_SW_TIME_USEC + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static u8 clk_sam9x5_slow_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return !!(readl(slowck->sckcr) & slowck->bits->cr_oscsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static const struct clk_ops sam9x5_slow_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .set_parent = clk_sam9x5_slow_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .get_parent = clk_sam9x5_slow_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) at91_clk_register_sam9x5_slow(void __iomem *sckcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) const char **parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) const struct clk_slow_bits *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct clk_sam9x5_slow *slowck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (!sckcr || !name || !parent_names || !num_parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) slowck = kzalloc(sizeof(*slowck), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (!slowck)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) init.ops = &sam9x5_slow_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) init.num_parents = num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) init.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) slowck->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) slowck->sckcr = sckcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) slowck->bits = bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) slowck->parent = !!(readl(sckcr) & slowck->bits->cr_oscsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) hw = &slowck->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ret = clk_hw_register(NULL, &slowck->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) kfree(slowck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static void at91_clk_unregister_sam9x5_slow(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) clk_hw_unregister(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) kfree(slowck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static void __init at91sam9x5_sckc_register(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) unsigned int rc_osc_startup_us,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) const struct clk_slow_bits *bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) const char *parent_names[2] = { "slow_rc_osc", "slow_osc" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) void __iomem *regbase = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct device_node *child = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) const char *xtal_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct clk_hw *slow_rc, *slow_osc, *slowck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) bool bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (!regbase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) slow_rc = at91_clk_register_slow_rc_osc(regbase, parent_names[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 32768, 50000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) rc_osc_startup_us, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (IS_ERR(slow_rc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) xtal_name = of_clk_get_parent_name(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (!xtal_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* DT backward compatibility */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) child = of_get_compatible_child(np, "atmel,at91sam9x5-clk-slow-osc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (!child)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) goto unregister_slow_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) xtal_name = of_clk_get_parent_name(child, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) bypass = of_property_read_bool(child, "atmel,osc-bypass");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) child = of_get_compatible_child(np, "atmel,at91sam9x5-clk-slow");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) bypass = of_property_read_bool(np, "atmel,osc-bypass");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (!xtal_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) goto unregister_slow_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) slow_osc = at91_clk_register_slow_osc(regbase, parent_names[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) xtal_name, 1200000, bypass, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (IS_ERR(slow_osc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) goto unregister_slow_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) slowck = at91_clk_register_sam9x5_slow(regbase, "slowck", parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 2, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (IS_ERR(slowck))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) goto unregister_slow_osc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* DT backward compatibility */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (child)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ret = of_clk_add_hw_provider(child, of_clk_hw_simple_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) slowck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, slowck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (WARN_ON(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) goto unregister_slowck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) unregister_slowck:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) at91_clk_unregister_sam9x5_slow(slowck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) unregister_slow_osc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) at91_clk_unregister_slow_osc(slow_osc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) unregister_slow_rc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) at91_clk_unregister_slow_rc_osc(slow_rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static const struct clk_slow_bits at91sam9x5_bits = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .cr_rcen = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .cr_osc32en = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .cr_osc32byp = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .cr_oscsel = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static void __init of_at91sam9x5_sckc_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) at91sam9x5_sckc_register(np, 75, &at91sam9x5_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) CLK_OF_DECLARE(at91sam9x5_clk_sckc, "atmel,at91sam9x5-sckc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) of_at91sam9x5_sckc_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static void __init of_sama5d3_sckc_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) at91sam9x5_sckc_register(np, 500, &at91sam9x5_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) CLK_OF_DECLARE(sama5d3_clk_sckc, "atmel,sama5d3-sckc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) of_sama5d3_sckc_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static const struct clk_slow_bits at91sam9x60_bits = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .cr_osc32en = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .cr_osc32byp = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .cr_oscsel = BIT(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static void __init of_sam9x60_sckc_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) void __iomem *regbase = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct clk_hw_onecell_data *clk_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct clk_hw *slow_rc, *slow_osc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) const char *xtal_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) const char *parent_names[2] = { "slow_rc_osc", "slow_osc" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) bool bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (!regbase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) slow_rc = clk_hw_register_fixed_rate_with_accuracy(NULL, parent_names[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) NULL, 0, 32768,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 93750000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (IS_ERR(slow_rc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) xtal_name = of_clk_get_parent_name(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (!xtal_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) goto unregister_slow_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) bypass = of_property_read_bool(np, "atmel,osc-bypass");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) slow_osc = at91_clk_register_slow_osc(regbase, parent_names[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) xtal_name, 5000000, bypass,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) &at91sam9x60_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (IS_ERR(slow_osc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) goto unregister_slow_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) clk_data = kzalloc(struct_size(clk_data, hws, 2), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (!clk_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) goto unregister_slow_osc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* MD_SLCK and TD_SLCK. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) clk_data->num = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) clk_data->hws[0] = clk_hw_register_fixed_rate(NULL, "md_slck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) parent_names[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 0, 32768);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (IS_ERR(clk_data->hws[0]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) goto clk_data_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) clk_data->hws[1] = at91_clk_register_sam9x5_slow(regbase, "td_slck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) parent_names, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) &at91sam9x60_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (IS_ERR(clk_data->hws[1]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) goto unregister_md_slck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (WARN_ON(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) goto unregister_td_slck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) unregister_td_slck:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) at91_clk_unregister_sam9x5_slow(clk_data->hws[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) unregister_md_slck:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) clk_hw_unregister(clk_data->hws[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) clk_data_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) kfree(clk_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) unregister_slow_osc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) at91_clk_unregister_slow_osc(slow_osc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) unregister_slow_rc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) clk_hw_unregister(slow_rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) CLK_OF_DECLARE(sam9x60_clk_sckc, "microchip,sam9x60-sckc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) of_sam9x60_sckc_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static int clk_sama5d4_slow_osc_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct clk_sama5d4_slow_osc *osc = to_clk_sama5d4_slow_osc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (osc->prepared)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * Assume that if it has already been selected (for example by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * bootloader), enough time has aready passed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if ((readl(osc->sckcr) & osc->bits->cr_oscsel)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) osc->prepared = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (system_state < SYSTEM_RUNNING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) udelay(osc->startup_usec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) usleep_range(osc->startup_usec, osc->startup_usec + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) osc->prepared = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static int clk_sama5d4_slow_osc_is_prepared(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct clk_sama5d4_slow_osc *osc = to_clk_sama5d4_slow_osc(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return osc->prepared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static const struct clk_ops sama5d4_slow_osc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .prepare = clk_sama5d4_slow_osc_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .is_prepared = clk_sama5d4_slow_osc_is_prepared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static const struct clk_slow_bits at91sama5d4_bits = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .cr_oscsel = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static void __init of_sama5d4_sckc_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) void __iomem *regbase = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct clk_hw *slow_rc, *slowck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct clk_sama5d4_slow_osc *osc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) const char *xtal_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) const char *parent_names[2] = { "slow_rc_osc", "slow_osc" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (!regbase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) slow_rc = clk_hw_register_fixed_rate_with_accuracy(NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) parent_names[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) NULL, 0, 32768,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 250000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (IS_ERR(slow_rc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) xtal_name = of_clk_get_parent_name(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) osc = kzalloc(sizeof(*osc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (!osc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) goto unregister_slow_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) init.name = parent_names[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) init.ops = &sama5d4_slow_osc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) init.parent_names = &xtal_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) init.flags = CLK_IGNORE_UNUSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) osc->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) osc->sckcr = regbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) osc->startup_usec = 1200000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) osc->bits = &at91sama5d4_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ret = clk_hw_register(NULL, &osc->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) goto free_slow_osc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) slowck = at91_clk_register_sam9x5_slow(regbase, "slowck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) parent_names, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) &at91sama5d4_bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (IS_ERR(slowck))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) goto unregister_slow_osc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, slowck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (WARN_ON(ret))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) goto unregister_slowck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) unregister_slowck:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) at91_clk_unregister_sam9x5_slow(slowck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) unregister_slow_osc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) clk_hw_unregister(&osc->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) free_slow_osc_data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) kfree(osc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) unregister_slow_rc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) clk_hw_unregister(slow_rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) CLK_OF_DECLARE(sama5d4_clk_sckc, "atmel,sama5d4-sckc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) of_sama5d4_sckc_setup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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