^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SAMA7G5 PMC code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <dt-bindings/clock/at91.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "pmc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SAMA7G5_INIT_TABLE(_table, _count) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u8 _i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) for (_i = 0; _i < (_count); _i++) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) (_table)[_i] = _i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SAMA7G5_FILL_TABLE(_to, _from, _count) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u8 _i; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) for (_i = 0; _i < (_count); _i++) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) (_to)[_i] = (_from)[_i]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static DEFINE_SPINLOCK(pmc_pll_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static DEFINE_SPINLOCK(pmc_mckX_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * PLL clocks identifiers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * @PLL_ID_CPU: CPU PLL identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * @PLL_ID_SYS: System PLL identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * @PLL_ID_DDR: DDR PLL identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @PLL_ID_IMG: Image subsystem PLL identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @PLL_ID_BAUD: Baud PLL identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @PLL_ID_AUDIO: Audio PLL identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @PLL_ID_ETH: Ethernet PLL identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) enum pll_ids {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PLL_ID_CPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PLL_ID_SYS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PLL_ID_DDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) PLL_ID_IMG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PLL_ID_BAUD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PLL_ID_AUDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) PLL_ID_ETH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) PLL_ID_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * PLL type identifiers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @PLL_TYPE_FRAC: fractional PLL identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @PLL_TYPE_DIV: divider PLL identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) enum pll_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PLL_TYPE_FRAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PLL_TYPE_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Layout for fractional PLLs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static const struct clk_pll_layout pll_layout_frac = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .mul_mask = GENMASK(31, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .frac_mask = GENMASK(21, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .mul_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .frac_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Layout for DIVPMC dividers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static const struct clk_pll_layout pll_layout_divpmc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .div_mask = GENMASK(7, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .endiv_mask = BIT(29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .div_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .endiv_shift = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Layout for DIVIO dividers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const struct clk_pll_layout pll_layout_divio = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .div_mask = GENMASK(19, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .endiv_mask = BIT(30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .div_shift = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .endiv_shift = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * PLL clocks description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * @n: clock name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * @p: clock parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @l: clock layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @t: clock type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @f: true if clock is critical and cannot be disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @eid: export index in sama7g5->chws[] array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) const char *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) const char *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) const struct clk_pll_layout *l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u8 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u8 c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u8 eid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) } sama7g5_plls[][PLL_ID_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) [PLL_ID_CPU] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { .n = "cpupll_fracck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .p = "mainck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .l = &pll_layout_frac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .t = PLL_TYPE_FRAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .c = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { .n = "cpupll_divpmcck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .p = "cpupll_fracck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .l = &pll_layout_divpmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .t = PLL_TYPE_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .c = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) [PLL_ID_SYS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { .n = "syspll_fracck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .p = "mainck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .l = &pll_layout_frac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .t = PLL_TYPE_FRAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .c = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { .n = "syspll_divpmcck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .p = "syspll_fracck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .l = &pll_layout_divpmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .t = PLL_TYPE_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .c = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) [PLL_ID_DDR] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { .n = "ddrpll_fracck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .p = "mainck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .l = &pll_layout_frac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .t = PLL_TYPE_FRAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .c = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { .n = "ddrpll_divpmcck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .p = "ddrpll_fracck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .l = &pll_layout_divpmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .t = PLL_TYPE_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .c = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) [PLL_ID_IMG] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { .n = "imgpll_fracck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .p = "mainck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .l = &pll_layout_frac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .t = PLL_TYPE_FRAC, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { .n = "imgpll_divpmcck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .p = "imgpll_fracck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .l = &pll_layout_divpmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .t = PLL_TYPE_DIV, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) [PLL_ID_BAUD] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { .n = "baudpll_fracck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .p = "mainck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .l = &pll_layout_frac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .t = PLL_TYPE_FRAC, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { .n = "baudpll_divpmcck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .p = "baudpll_fracck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .l = &pll_layout_divpmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .t = PLL_TYPE_DIV, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) [PLL_ID_AUDIO] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { .n = "audiopll_fracck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .p = "main_xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .l = &pll_layout_frac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .t = PLL_TYPE_FRAC, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { .n = "audiopll_divpmcck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .p = "audiopll_fracck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .l = &pll_layout_divpmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .t = PLL_TYPE_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .eid = PMC_I2S0_MUX, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { .n = "audiopll_diviock",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .p = "audiopll_fracck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .l = &pll_layout_divio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .t = PLL_TYPE_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .eid = PMC_I2S1_MUX, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) [PLL_ID_ETH] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { .n = "ethpll_fracck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .p = "main_xtal",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .l = &pll_layout_frac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .t = PLL_TYPE_FRAC, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { .n = "ethpll_divpmcck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .p = "ethpll_fracck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .l = &pll_layout_divpmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .t = PLL_TYPE_DIV, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * Master clock (MCK[1..4]) description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * @n: clock name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * @ep: extra parents names array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * @ep_chg_chg_id: index in parents array that specifies the changeable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * @ep_count: extra parents count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * @ep_mux_table: mux table for extra parents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * @id: clock id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * @c: true if clock is critical and cannot be disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) const char *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) const char *ep[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int ep_chg_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u8 ep_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u8 ep_mux_table[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u8 c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) } sama7g5_mckx[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { .n = "mck1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .ep = { "syspll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .ep_mux_table = { 5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .ep_count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .ep_chg_id = INT_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .c = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { .n = "mck2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .id = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .ep = { "ddrpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .ep_mux_table = { 6, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .ep_count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .ep_chg_id = INT_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .c = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { .n = "mck3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .id = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .ep = { "syspll_divpmcck", "ddrpll_divpmcck", "imgpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .ep_mux_table = { 5, 6, 7, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .ep_count = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .ep_chg_id = 6, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { .n = "mck4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .id = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .ep = { "syspll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .ep_mux_table = { 5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .ep_count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .ep_chg_id = INT_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .c = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * System clock description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * @n: clock name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * @p: clock parent name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * @id: clock id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) const char *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) const char *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) } sama7g5_systemck[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { .n = "pck0", .p = "prog0", .id = 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { .n = "pck1", .p = "prog1", .id = 9, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { .n = "pck2", .p = "prog2", .id = 10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) { .n = "pck3", .p = "prog3", .id = 11, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) { .n = "pck4", .p = "prog4", .id = 12, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) { .n = "pck5", .p = "prog5", .id = 13, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) { .n = "pck6", .p = "prog6", .id = 14, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) { .n = "pck7", .p = "prog7", .id = 15, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Mux table for programmable clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static u32 sama7g5_prog_mux_table[] = { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * Peripheral clock description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * @n: clock name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * @p: clock parent name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * @r: clock range values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * @id: clock id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * @chgp: index in parent array of the changeable parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) const char *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) const char *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct clk_range r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u8 chgp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) } sama7g5_periphck[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { .n = "pioA_clk", .p = "mck0", .id = 11, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) { .n = "sfr_clk", .p = "mck1", .id = 19, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { .n = "hsmc_clk", .p = "mck1", .id = 21, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { .n = "xdmac0_clk", .p = "mck1", .id = 22, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { .n = "xdmac1_clk", .p = "mck1", .id = 23, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) { .n = "xdmac2_clk", .p = "mck1", .id = 24, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) { .n = "acc_clk", .p = "mck1", .id = 25, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) { .n = "aes_clk", .p = "mck1", .id = 27, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) { .n = "tzaesbasc_clk", .p = "mck1", .id = 28, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { .n = "asrc_clk", .p = "mck1", .id = 30, .r = { .max = 200000000, }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) { .n = "cpkcc_clk", .p = "mck0", .id = 32, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) { .n = "csi_clk", .p = "mck3", .id = 33, .r = { .max = 266000000, }, .chgp = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) { .n = "csi2dc_clk", .p = "mck3", .id = 34, .r = { .max = 266000000, }, .chgp = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { .n = "eic_clk", .p = "mck1", .id = 37, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { .n = "flex0_clk", .p = "mck1", .id = 38, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) { .n = "flex1_clk", .p = "mck1", .id = 39, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { .n = "flex2_clk", .p = "mck1", .id = 40, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { .n = "flex3_clk", .p = "mck1", .id = 41, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) { .n = "flex4_clk", .p = "mck1", .id = 42, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) { .n = "flex5_clk", .p = "mck1", .id = 43, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { .n = "flex6_clk", .p = "mck1", .id = 44, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { .n = "flex7_clk", .p = "mck1", .id = 45, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { .n = "flex8_clk", .p = "mck1", .id = 46, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { .n = "flex9_clk", .p = "mck1", .id = 47, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) { .n = "flex10_clk", .p = "mck1", .id = 48, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { .n = "flex11_clk", .p = "mck1", .id = 49, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { .n = "gmac0_clk", .p = "mck1", .id = 51, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { .n = "gmac1_clk", .p = "mck1", .id = 52, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { .n = "icm_clk", .p = "mck1", .id = 55, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { .n = "isc_clk", .p = "mck3", .id = 56, .r = { .max = 266000000, }, .chgp = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) { .n = "i2smcc0_clk", .p = "mck1", .id = 57, .r = { .max = 200000000, }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { .n = "i2smcc1_clk", .p = "mck1", .id = 58, .r = { .max = 200000000, }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) { .n = "matrix_clk", .p = "mck1", .id = 60, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { .n = "mcan0_clk", .p = "mck1", .id = 61, .r = { .max = 200000000, }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { .n = "mcan1_clk", .p = "mck1", .id = 62, .r = { .max = 200000000, }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { .n = "mcan2_clk", .p = "mck1", .id = 63, .r = { .max = 200000000, }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) { .n = "mcan3_clk", .p = "mck1", .id = 64, .r = { .max = 200000000, }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { .n = "mcan4_clk", .p = "mck1", .id = 65, .r = { .max = 200000000, }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { .n = "mcan5_clk", .p = "mck1", .id = 66, .r = { .max = 200000000, }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { .n = "pdmc0_clk", .p = "mck1", .id = 68, .r = { .max = 200000000, }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { .n = "pdmc1_clk", .p = "mck1", .id = 69, .r = { .max = 200000000, }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { .n = "pit64b0_clk", .p = "mck1", .id = 70, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) { .n = "pit64b1_clk", .p = "mck1", .id = 71, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) { .n = "pit64b2_clk", .p = "mck1", .id = 72, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) { .n = "pit64b3_clk", .p = "mck1", .id = 73, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { .n = "pit64b4_clk", .p = "mck1", .id = 74, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) { .n = "pit64b5_clk", .p = "mck1", .id = 75, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) { .n = "pwm_clk", .p = "mck1", .id = 77, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) { .n = "qspi0_clk", .p = "mck1", .id = 78, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { .n = "qspi1_clk", .p = "mck1", .id = 79, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) { .n = "sdmmc0_clk", .p = "mck1", .id = 80, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) { .n = "sdmmc1_clk", .p = "mck1", .id = 81, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) { .n = "sdmmc2_clk", .p = "mck1", .id = 82, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) { .n = "sha_clk", .p = "mck1", .id = 83, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) { .n = "spdifrx_clk", .p = "mck1", .id = 84, .r = { .max = 200000000, }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) { .n = "spdiftx_clk", .p = "mck1", .id = 85, .r = { .max = 200000000, }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) { .n = "ssc0_clk", .p = "mck1", .id = 86, .r = { .max = 200000000, }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) { .n = "ssc1_clk", .p = "mck1", .id = 87, .r = { .max = 200000000, }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) { .n = "tcb0_ch0_clk", .p = "mck1", .id = 88, .r = { .max = 200000000, }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) { .n = "tcb0_ch1_clk", .p = "mck1", .id = 89, .r = { .max = 200000000, }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) { .n = "tcb0_ch2_clk", .p = "mck1", .id = 90, .r = { .max = 200000000, }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { .n = "tcb1_ch0_clk", .p = "mck1", .id = 91, .r = { .max = 200000000, }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) { .n = "tcb1_ch1_clk", .p = "mck1", .id = 92, .r = { .max = 200000000, }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { .n = "tcb1_ch2_clk", .p = "mck1", .id = 93, .r = { .max = 200000000, }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) { .n = "tcpca_clk", .p = "mck1", .id = 94, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) { .n = "tcpcb_clk", .p = "mck1", .id = 95, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) { .n = "tdes_clk", .p = "mck1", .id = 96, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) { .n = "trng_clk", .p = "mck1", .id = 97, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) { .n = "udphsa_clk", .p = "mck1", .id = 104, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) { .n = "udphsb_clk", .p = "mck1", .id = 105, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) { .n = "uhphs_clk", .p = "mck1", .id = 106, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * Generic clock description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * @n: clock name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * @pp: PLL parents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * @pp_mux_table: PLL parents mux table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * @r: clock output range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * @pp_chg_id: id in parrent array of changeable PLL parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * @pp_count: PLL parents count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * @id: clock id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) const char *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) const char *pp[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) const char pp_mux_table[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct clk_range r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int pp_chg_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u8 pp_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) } sama7g5_gck[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) { .n = "adc_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .id = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .r = { .max = 100000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .pp = { "syspll_divpmcck", "imgpll_divpmcck", "audiopll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .pp_mux_table = { 5, 7, 9, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .pp_count = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) { .n = "asrc_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .id = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .r = { .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .pp = { "audiopll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .pp_mux_table = { 9, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .pp_count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .pp_chg_id = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) { .n = "csi_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .id = 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .r = { .max = 27000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .pp = { "ddrpll_divpmcck", "imgpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .pp_mux_table = { 6, 7, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) { .n = "flex0_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .id = 38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .r = { .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .pp_mux_table = { 5, 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) { .n = "flex1_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .id = 39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .r = { .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .pp_mux_table = { 5, 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) { .n = "flex2_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .id = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .r = { .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .pp_mux_table = { 5, 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) { .n = "flex3_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .id = 41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .r = { .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .pp_mux_table = { 5, 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) { .n = "flex4_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .id = 42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .r = { .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .pp_mux_table = { 5, 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) { .n = "flex5_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .id = 43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .r = { .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .pp_mux_table = { 5, 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) { .n = "flex6_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .id = 44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .r = { .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .pp_mux_table = { 5, 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) { .n = "flex7_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .id = 45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .r = { .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .pp_mux_table = { 5, 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) { .n = "flex8_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .id = 46,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .r = { .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .pp_mux_table = { 5, 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) { .n = "flex9_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .id = 47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .r = { .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .pp_mux_table = { 5, 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) { .n = "flex10_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .id = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .r = { .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .pp_mux_table = { 5, 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) { .n = "flex11_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .id = 49,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .r = { .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .pp_mux_table = { 5, 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) { .n = "gmac0_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .id = 51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .r = { .max = 125000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .pp = { "ethpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .pp_mux_table = { 10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .pp_count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .pp_chg_id = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) { .n = "gmac1_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .id = 52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .r = { .max = 50000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .pp = { "ethpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .pp_mux_table = { 10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .pp_count = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) { .n = "gmac0_tsu_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .id = 53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .r = { .max = 300000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .pp = { "audiopll_divpmcck", "ethpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .pp_mux_table = { 9, 10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) { .n = "gmac1_tsu_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .id = 54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .r = { .max = 300000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .pp = { "audiopll_divpmcck", "ethpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .pp_mux_table = { 9, 10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) { .n = "i2smcc0_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .id = 57,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .r = { .max = 100000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .pp = { "syspll_divpmcck", "audiopll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .pp_mux_table = { 5, 9, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .pp_chg_id = 5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) { .n = "i2smcc1_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .id = 58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .r = { .max = 100000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .pp = { "syspll_divpmcck", "audiopll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .pp_mux_table = { 5, 9, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .pp_chg_id = 5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) { .n = "mcan0_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .id = 61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .r = { .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .pp_mux_table = { 5, 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) { .n = "mcan1_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .id = 62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .r = { .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .pp_mux_table = { 5, 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) { .n = "mcan2_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .id = 63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .r = { .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .pp_mux_table = { 5, 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) { .n = "mcan3_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .id = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .r = { .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .pp_mux_table = { 5, 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) { .n = "mcan4_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .id = 65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .r = { .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .pp_mux_table = { 5, 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) { .n = "mcan5_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .id = 66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .r = { .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .pp_mux_table = { 5, 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) { .n = "pdmc0_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .id = 68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .r = { .max = 50000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .pp = { "syspll_divpmcck", "audiopll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .pp_mux_table = { 5, 9, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) { .n = "pdmc1_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .id = 69,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .r = { .max = 50000000, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .pp = { "syspll_divpmcck", "audiopll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .pp_mux_table = { 5, 9, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) { .n = "pit64b0_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .id = 70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .r = { .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) "audiopll_divpmcck", "ethpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .pp_mux_table = { 5, 7, 8, 9, 10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .pp_count = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) { .n = "pit64b1_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .id = 71,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .r = { .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) "audiopll_divpmcck", "ethpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .pp_mux_table = { 5, 7, 8, 9, 10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .pp_count = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) { .n = "pit64b2_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .id = 72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .r = { .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) "audiopll_divpmcck", "ethpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .pp_mux_table = { 5, 7, 8, 9, 10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .pp_count = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) { .n = "pit64b3_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .id = 73,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .r = { .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) "audiopll_divpmcck", "ethpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .pp_mux_table = { 5, 7, 8, 9, 10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .pp_count = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) { .n = "pit64b4_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .id = 74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .r = { .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) "audiopll_divpmcck", "ethpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .pp_mux_table = { 5, 7, 8, 9, 10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .pp_count = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) { .n = "pit64b5_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .id = 75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .r = { .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) "audiopll_divpmcck", "ethpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .pp_mux_table = { 5, 7, 8, 9, 10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .pp_count = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) { .n = "qspi0_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .id = 78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .r = { .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .pp_mux_table = { 5, 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) { .n = "qspi1_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .id = 79,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .r = { .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .pp_mux_table = { 5, 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) { .n = "sdmmc0_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .id = 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .r = { .max = 208000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .pp_mux_table = { 5, 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .pp_chg_id = 5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) { .n = "sdmmc1_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .id = 81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .r = { .max = 208000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .pp_mux_table = { 5, 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .pp_chg_id = 5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) { .n = "sdmmc2_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .id = 82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .r = { .max = 208000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .pp = { "syspll_divpmcck", "baudpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .pp_mux_table = { 5, 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .pp_chg_id = 5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) { .n = "spdifrx_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .id = 84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .r = { .max = 150000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .pp = { "syspll_divpmcck", "audiopll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .pp_mux_table = { 5, 9, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .pp_chg_id = 5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) { .n = "spdiftx_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .id = 85,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .r = { .max = 25000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .pp = { "syspll_divpmcck", "audiopll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .pp_mux_table = { 5, 9, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .pp_count = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .pp_chg_id = 5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) { .n = "tcb0_ch0_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .id = 88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .r = { .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) "audiopll_divpmcck", "ethpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .pp_mux_table = { 5, 7, 8, 9, 10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .pp_count = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) { .n = "tcb1_ch0_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .id = 91,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .r = { .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .pp = { "syspll_divpmcck", "imgpll_divpmcck", "baudpll_divpmcck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) "audiopll_divpmcck", "ethpll_divpmcck", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .pp_mux_table = { 5, 7, 8, 9, 10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .pp_count = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) { .n = "tcpca_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .id = 94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .r = { .max = 32768, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) { .n = "tcpcb_gclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .id = 95,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .r = { .max = 32768, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .pp_chg_id = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* PLL output range. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static const struct clk_range pll_outputs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) { .min = 2343750, .max = 1200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /* PLL characteristics. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static const struct clk_pll_characteristics pll_characteristics = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .input = { .min = 12000000, .max = 50000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .num_output = ARRAY_SIZE(pll_outputs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .output = pll_outputs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* MCK0 characteristics. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static const struct clk_master_characteristics mck0_characteristics = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .output = { .min = 140000000, .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .divisors = { 1, 2, 4, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .have_div3_pres = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* MCK0 layout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static const struct clk_master_layout mck0_layout = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .mask = 0x373,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .pres_shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .offset = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* Programmable clock layout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static const struct clk_programmable_layout programmable_layout = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .pres_mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .pres_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .css_mask = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .have_slck_mck = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .is_pres_direct = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /* Peripheral clock layout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static const struct clk_pcr_layout sama7g5_pcr_layout = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .offset = 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .cmd = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .gckcss_mask = GENMASK(12, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .pid_mask = GENMASK(6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static void __init sama7g5_pmc_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) const char *td_slck_name, *md_slck_name, *mainxtal_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct pmc_data *sama7g5_pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) const char *parent_names[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) void **alloc_mem = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) int alloc_mem_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) bool bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) i = of_property_match_string(np, "clock-names", "td_slck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) td_slck_name = of_clk_get_parent_name(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) i = of_property_match_string(np, "clock-names", "md_slck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) md_slck_name = of_clk_get_parent_name(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) i = of_property_match_string(np, "clock-names", "main_xtal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) mainxtal_name = of_clk_get_parent_name(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) regmap = device_node_to_regmap(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) sama7g5_pmc = pmc_data_allocate(PMC_I2S1_MUX + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) nck(sama7g5_systemck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) nck(sama7g5_periphck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) nck(sama7g5_gck), 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (!sama7g5_pmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) alloc_mem = kmalloc(sizeof(void *) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) (ARRAY_SIZE(sama7g5_mckx) + ARRAY_SIZE(sama7g5_gck)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (!alloc_mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) 50000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) bypass = of_property_read_bool(np, "atmel,osc-bypass");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) bypass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) parent_names[0] = "main_rc_osc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) parent_names[1] = "main_osc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) sama7g5_pmc->chws[PMC_MAIN] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) for (i = 0; i < PLL_ID_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) for (j = 0; j < 3; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) struct clk_hw *parent_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (!sama7g5_plls[i][j].n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) switch (sama7g5_plls[i][j].t) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) case PLL_TYPE_FRAC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (!strcmp(sama7g5_plls[i][j].p, "mainck"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) parent_hw = sama7g5_pmc->chws[PMC_MAIN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) parent_hw = __clk_get_hw(of_clk_get_by_name(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) sama7g5_plls[i][j].p));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) hw = sam9x60_clk_register_frac_pll(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) &pmc_pll_lock, sama7g5_plls[i][j].n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) sama7g5_plls[i][j].p, parent_hw, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) &pll_characteristics,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) sama7g5_plls[i][j].l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) sama7g5_plls[i][j].c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) case PLL_TYPE_DIV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) hw = sam9x60_clk_register_div_pll(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) &pmc_pll_lock, sama7g5_plls[i][j].n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) sama7g5_plls[i][j].p, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) &pll_characteristics,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) sama7g5_plls[i][j].l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) sama7g5_plls[i][j].c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (sama7g5_plls[i][j].eid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) sama7g5_pmc->chws[sama7g5_plls[i][j].eid] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) parent_names[0] = md_slck_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) parent_names[1] = "mainck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) parent_names[2] = "cpupll_divpmcck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) parent_names[3] = "syspll_divpmcck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) hw = at91_clk_register_master(regmap, "mck0", 4, parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) &mck0_layout, &mck0_characteristics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) sama7g5_pmc->chws[PMC_MCK] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) parent_names[0] = md_slck_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) parent_names[1] = td_slck_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) parent_names[2] = "mainck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) parent_names[3] = "mck0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) for (i = 0; i < ARRAY_SIZE(sama7g5_mckx); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) u8 num_parents = 4 + sama7g5_mckx[i].ep_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) u32 *mux_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) mux_table = kmalloc_array(num_parents, sizeof(*mux_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (!mux_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) SAMA7G5_INIT_TABLE(mux_table, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) SAMA7G5_FILL_TABLE(&mux_table[4], sama7g5_mckx[i].ep_mux_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) sama7g5_mckx[i].ep_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) SAMA7G5_FILL_TABLE(&parent_names[4], sama7g5_mckx[i].ep,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) sama7g5_mckx[i].ep_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) hw = at91_clk_sama7g5_register_master(regmap, sama7g5_mckx[i].n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) num_parents, parent_names, mux_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) &pmc_mckX_lock, sama7g5_mckx[i].id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) sama7g5_mckx[i].c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) sama7g5_mckx[i].ep_chg_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) alloc_mem[alloc_mem_size++] = mux_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) hw = at91_clk_sama7g5_register_utmi(regmap, "utmick", "main_xtal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) sama7g5_pmc->chws[PMC_UTMI] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) parent_names[0] = md_slck_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) parent_names[1] = td_slck_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) parent_names[2] = "mainck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) parent_names[3] = "mck0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) parent_names[4] = "syspll_divpmcck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) parent_names[5] = "ddrpll_divpmcck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) parent_names[6] = "imgpll_divpmcck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) parent_names[7] = "baudpll_divpmcck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) parent_names[8] = "audiopll_divpmcck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) parent_names[9] = "ethpll_divpmcck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) char name[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) snprintf(name, sizeof(name), "prog%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) hw = at91_clk_register_programmable(regmap, name, parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) 10, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) &programmable_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) sama7g5_prog_mux_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) sama7g5_pmc->pchws[i] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) for (i = 0; i < ARRAY_SIZE(sama7g5_systemck); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) hw = at91_clk_register_system(regmap, sama7g5_systemck[i].n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) sama7g5_systemck[i].p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) sama7g5_systemck[i].id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) sama7g5_pmc->shws[sama7g5_systemck[i].id] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) for (i = 0; i < ARRAY_SIZE(sama7g5_periphck); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) &sama7g5_pcr_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) sama7g5_periphck[i].n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) sama7g5_periphck[i].p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) sama7g5_periphck[i].id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) &sama7g5_periphck[i].r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) sama7g5_periphck[i].chgp ? 0 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) INT_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) sama7g5_pmc->phws[sama7g5_periphck[i].id] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) parent_names[0] = md_slck_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) parent_names[1] = td_slck_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) parent_names[2] = "mainck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) parent_names[3] = "mck0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) for (i = 0; i < ARRAY_SIZE(sama7g5_gck); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) u8 num_parents = 4 + sama7g5_gck[i].pp_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) u32 *mux_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) mux_table = kmalloc_array(num_parents, sizeof(*mux_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (!mux_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) SAMA7G5_INIT_TABLE(mux_table, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) SAMA7G5_FILL_TABLE(&mux_table[4], sama7g5_gck[i].pp_mux_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) sama7g5_gck[i].pp_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) SAMA7G5_FILL_TABLE(&parent_names[4], sama7g5_gck[i].pp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) sama7g5_gck[i].pp_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) &sama7g5_pcr_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) sama7g5_gck[i].n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) parent_names, mux_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) sama7g5_gck[i].id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) &sama7g5_gck[i].r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) sama7g5_gck[i].pp_chg_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) sama7g5_pmc->ghws[sama7g5_gck[i].id] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) alloc_mem[alloc_mem_size++] = mux_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama7g5_pmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) err_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (alloc_mem) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) for (i = 0; i < alloc_mem_size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) kfree(alloc_mem[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) kfree(alloc_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) kfree(sama7g5_pmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) /* Some clks are used for a clocksource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) CLK_OF_DECLARE(sama7g5_pmc, "microchip,sama7g5-pmc", sama7g5_pmc_setup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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