Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <dt-bindings/clock/at91.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include "pmc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) static const struct clk_master_characteristics mck_characteristics = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 	.output = { .min = 125000000, .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 	.divisors = { 1, 2, 4, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) static u8 plla_out[] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) static u16 plla_icpll[] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) static const struct clk_range plla_outputs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	{ .min = 600000000, .max = 1200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) static const struct clk_pll_characteristics plla_characteristics = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	.input = { .min = 12000000, .max = 12000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	.num_output = ARRAY_SIZE(plla_outputs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	.output = plla_outputs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	.icpll = plla_icpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	.out = plla_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static const struct clk_pcr_layout sama5d4_pcr_layout = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	.offset = 0x10c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	.cmd = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	.pid_mask = GENMASK(6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	char *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	char *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) } sama5d4_systemck[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	{ .n = "ddrck", .p = "masterck", .id = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	{ .n = "lcdck", .p = "masterck", .id = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	{ .n = "smdck", .p = "smdclk",   .id = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	{ .n = "uhpck", .p = "usbck",    .id = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	{ .n = "udpck", .p = "usbck",    .id = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	{ .n = "pck0",  .p = "prog0",    .id = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	{ .n = "pck1",  .p = "prog1",    .id = 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	{ .n = "pck2",  .p = "prog2",    .id = 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	char *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) } sama5d4_periph32ck[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	{ .n = "pioD_clk", .id = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	{ .n = "usart0_clk", .id = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	{ .n = "usart1_clk", .id = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	{ .n = "icm_clk", .id = 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	{ .n = "aes_clk", .id = 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	{ .n = "tdes_clk", .id = 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	{ .n = "sha_clk", .id = 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	{ .n = "matrix1_clk", .id = 17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	{ .n = "hsmc_clk", .id = 22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	{ .n = "pioA_clk", .id = 23 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	{ .n = "pioB_clk", .id = 24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	{ .n = "pioC_clk", .id = 25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	{ .n = "pioE_clk", .id = 26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	{ .n = "uart0_clk", .id = 27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	{ .n = "uart1_clk", .id = 28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	{ .n = "usart2_clk", .id = 29 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	{ .n = "usart3_clk", .id = 30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	{ .n = "usart4_clk", .id = 31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	{ .n = "twi0_clk", .id = 32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	{ .n = "twi1_clk", .id = 33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	{ .n = "twi2_clk", .id = 34 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	{ .n = "mci0_clk", .id = 35 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	{ .n = "mci1_clk", .id = 36 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	{ .n = "spi0_clk", .id = 37 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	{ .n = "spi1_clk", .id = 38 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	{ .n = "spi2_clk", .id = 39 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	{ .n = "tcb0_clk", .id = 40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	{ .n = "tcb1_clk", .id = 41 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	{ .n = "tcb2_clk", .id = 42 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	{ .n = "pwm_clk", .id = 43 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	{ .n = "adc_clk", .id = 44 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	{ .n = "dbgu_clk", .id = 45 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	{ .n = "uhphs_clk", .id = 46 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	{ .n = "udphs_clk", .id = 47 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	{ .n = "ssc0_clk", .id = 48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	{ .n = "ssc1_clk", .id = 49 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	{ .n = "trng_clk", .id = 53 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	{ .n = "macb0_clk", .id = 54 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	{ .n = "macb1_clk", .id = 55 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	{ .n = "fuse_clk", .id = 57 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	{ .n = "securam_clk", .id = 59 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	{ .n = "smd_clk", .id = 61 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	{ .n = "twi3_clk", .id = 62 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	{ .n = "catb_clk", .id = 63 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	char *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) } sama5d4_periphck[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	{ .n = "dma0_clk", .id = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	{ .n = "cpkcc_clk", .id = 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	{ .n = "aesb_clk", .id = 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	{ .n = "mpddr_clk", .id = 16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	{ .n = "matrix0_clk", .id = 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	{ .n = "vdec_clk", .id = 19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	{ .n = "dma1_clk", .id = 50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	{ .n = "lcdc_clk", .id = 51 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	{ .n = "isi_clk", .id = 52 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static void __init sama5d4_pmc_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	struct clk_range range = CLK_RANGE(0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	const char *slck_name, *mainxtal_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	struct pmc_data *sama5d4_pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	const char *parent_names[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	bool bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	i = of_property_match_string(np, "clock-names", "slow_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	slck_name = of_clk_get_parent_name(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	i = of_property_match_string(np, "clock-names", "main_xtal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	mainxtal_name = of_clk_get_parent_name(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	regmap = device_node_to_regmap(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	sama5d4_pmc = pmc_data_allocate(PMC_PLLACK + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 					nck(sama5d4_systemck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 					nck(sama5d4_periph32ck), 0, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	if (!sama5d4_pmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 					   100000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	bypass = of_property_read_bool(np, "atmel,osc-bypass");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 					bypass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	parent_names[0] = "main_rc_osc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	parent_names[1] = "main_osc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 				   &sama5d3_pll_layout, &plla_characteristics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	sama5d4_pmc->chws[PMC_PLLACK] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	sama5d4_pmc->chws[PMC_UTMI] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	parent_names[0] = slck_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	parent_names[1] = "mainck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	parent_names[2] = "plladivck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	parent_names[3] = "utmick";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 				      &at91sam9x5_master_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 				      &mck_characteristics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	sama5d4_pmc->chws[PMC_MCK] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	sama5d4_pmc->chws[PMC_MCK2] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	parent_names[0] = "plladivck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	parent_names[1] = "utmick";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	parent_names[0] = "plladivck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	parent_names[1] = "utmick";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	hw = at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	parent_names[0] = slck_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	parent_names[1] = "mainck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	parent_names[2] = "plladivck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	parent_names[3] = "utmick";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	parent_names[4] = "masterck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		char name[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		snprintf(name, sizeof(name), "prog%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		hw = at91_clk_register_programmable(regmap, name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 						    parent_names, 5, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 						    &at91sam9x5_programmable_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 						    NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		sama5d4_pmc->pchws[i] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	for (i = 0; i < ARRAY_SIZE(sama5d4_systemck); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		hw = at91_clk_register_system(regmap, sama5d4_systemck[i].n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 					      sama5d4_systemck[i].p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 					      sama5d4_systemck[i].id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		sama5d4_pmc->shws[sama5d4_systemck[i].id] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	for (i = 0; i < ARRAY_SIZE(sama5d4_periphck); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 							 &sama5d4_pcr_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 							 sama5d4_periphck[i].n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 							 "masterck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 							 sama5d4_periphck[i].id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 							 &range, INT_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		sama5d4_pmc->phws[sama5d4_periphck[i].id] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	for (i = 0; i < ARRAY_SIZE(sama5d4_periph32ck); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 							 &sama5d4_pcr_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 							 sama5d4_periph32ck[i].n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 							 "h32mxck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 							 sama5d4_periph32ck[i].id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 							 &range, INT_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 			goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		sama5d4_pmc->phws[sama5d4_periph32ck[i].id] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama5d4_pmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) err_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	kfree(sama5d4_pmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) CLK_OF_DECLARE_DRIVER(sama5d4_pmc, "atmel,sama5d4-pmc", sama5d4_pmc_setup);