Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <dt-bindings/clock/at91.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include "pmc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) static const struct clk_master_characteristics mck_characteristics = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 	.output = { .min = 124000000, .max = 166000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 	.divisors = { 1, 2, 4, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) static u8 plla_out[] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) static u16 plla_icpll[] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) static const struct clk_range plla_outputs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	{ .min = 600000000, .max = 1200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) static const struct clk_pll_characteristics plla_characteristics = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	.input = { .min = 12000000, .max = 24000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	.num_output = ARRAY_SIZE(plla_outputs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	.output = plla_outputs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	.icpll = plla_icpll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	.out = plla_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static const struct clk_pcr_layout sama5d2_pcr_layout = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	.offset = 0x10c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	.cmd = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	.gckcss_mask = GENMASK(10, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	.pid_mask = GENMASK(6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	char *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	char *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) } sama5d2_systemck[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	{ .n = "ddrck", .p = "masterck", .id = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	{ .n = "lcdck", .p = "masterck", .id = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	{ .n = "uhpck", .p = "usbck",    .id = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	{ .n = "udpck", .p = "usbck",    .id = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	{ .n = "pck0",  .p = "prog0",    .id = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	{ .n = "pck1",  .p = "prog1",    .id = 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	{ .n = "pck2",  .p = "prog2",    .id = 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	{ .n = "iscck", .p = "masterck", .id = 18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	char *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	struct clk_range r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) } sama5d2_periph32ck[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	{ .n = "macb0_clk",   .id = 5,  .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	{ .n = "tdes_clk",    .id = 11, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	{ .n = "matrix1_clk", .id = 14, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	{ .n = "hsmc_clk",    .id = 17, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	{ .n = "pioA_clk",    .id = 18, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	{ .n = "flx0_clk",    .id = 19, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	{ .n = "flx1_clk",    .id = 20, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	{ .n = "flx2_clk",    .id = 21, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	{ .n = "flx3_clk",    .id = 22, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	{ .n = "flx4_clk",    .id = 23, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	{ .n = "uart0_clk",   .id = 24, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	{ .n = "uart1_clk",   .id = 25, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	{ .n = "uart2_clk",   .id = 26, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	{ .n = "uart3_clk",   .id = 27, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	{ .n = "uart4_clk",   .id = 28, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	{ .n = "twi0_clk",    .id = 29, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	{ .n = "twi1_clk",    .id = 30, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	{ .n = "spi0_clk",    .id = 33, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	{ .n = "spi1_clk",    .id = 34, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	{ .n = "tcb0_clk",    .id = 35, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	{ .n = "tcb1_clk",    .id = 36, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	{ .n = "pwm_clk",     .id = 38, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	{ .n = "adc_clk",     .id = 40, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	{ .n = "uhphs_clk",   .id = 41, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	{ .n = "udphs_clk",   .id = 42, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	{ .n = "ssc0_clk",    .id = 43, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	{ .n = "ssc1_clk",    .id = 44, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	{ .n = "trng_clk",    .id = 47, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	{ .n = "pdmic_clk",   .id = 48, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	{ .n = "securam_clk", .id = 51, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	{ .n = "i2s0_clk",    .id = 54, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	{ .n = "i2s1_clk",    .id = 55, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	{ .n = "can0_clk",    .id = 56, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	{ .n = "can1_clk",    .id = 57, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	{ .n = "ptc_clk",     .id = 58, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	{ .n = "classd_clk",  .id = 59, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	char *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) } sama5d2_periphck[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	{ .n = "dma0_clk",    .id = 6, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	{ .n = "dma1_clk",    .id = 7, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	{ .n = "aes_clk",     .id = 9, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	{ .n = "aesb_clk",    .id = 10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	{ .n = "sha_clk",     .id = 12, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	{ .n = "mpddr_clk",   .id = 13, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	{ .n = "matrix0_clk", .id = 15, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	{ .n = "sdmmc0_hclk", .id = 31, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	{ .n = "sdmmc1_hclk", .id = 32, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	{ .n = "lcdc_clk",    .id = 45, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	{ .n = "isc_clk",     .id = 46, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	{ .n = "qspi0_clk",   .id = 52, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	{ .n = "qspi1_clk",   .id = 53, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	char *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct clk_range r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	int chg_pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) } sama5d2_gck[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	{ .n = "sdmmc0_gclk", .id = 31, .chg_pid = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	{ .n = "sdmmc1_gclk", .id = 32, .chg_pid = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	{ .n = "tcb0_gclk",   .id = 35, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	{ .n = "tcb1_gclk",   .id = 36, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	{ .n = "pwm_gclk",    .id = 38, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	{ .n = "isc_gclk",    .id = 46, .chg_pid = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	{ .n = "pdmic_gclk",  .id = 48, .chg_pid = INT_MIN, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	{ .n = "i2s0_gclk",   .id = 54, .chg_pid = 5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	{ .n = "i2s1_gclk",   .id = 55, .chg_pid = 5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	{ .n = "can0_gclk",   .id = 56, .chg_pid = INT_MIN, .r = { .min = 0, .max = 80000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	{ .n = "can1_gclk",   .id = 57, .chg_pid = INT_MIN, .r = { .min = 0, .max = 80000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	{ .n = "classd_gclk", .id = 59, .chg_pid = 5, .r = { .min = 0, .max = 100000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static const struct clk_programmable_layout sama5d2_programmable_layout = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.pres_mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.pres_shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.css_mask = 0x7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.have_slck_mck = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.is_pres_direct = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static void __init sama5d2_pmc_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	struct clk_range range = CLK_RANGE(0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	const char *slck_name, *mainxtal_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	struct pmc_data *sama5d2_pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	const char *parent_names[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	struct regmap *regmap, *regmap_sfr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	bool bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	i = of_property_match_string(np, "clock-names", "slow_clk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	slck_name = of_clk_get_parent_name(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	i = of_property_match_string(np, "clock-names", "main_xtal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	mainxtal_name = of_clk_get_parent_name(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	regmap = device_node_to_regmap(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	sama5d2_pmc = pmc_data_allocate(PMC_AUDIOPLLCK + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 					nck(sama5d2_systemck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 					nck(sama5d2_periph32ck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 					nck(sama5d2_gck), 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	if (!sama5d2_pmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 					   100000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	bypass = of_property_read_bool(np, "atmel,osc-bypass");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 					bypass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	parent_names[0] = "main_rc_osc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	parent_names[1] = "main_osc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	sama5d2_pmc->chws[PMC_MAIN] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 				   &sama5d3_pll_layout, &plla_characteristics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	sama5d2_pmc->chws[PMC_PLLACK] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	hw = at91_clk_register_audio_pll_frac(regmap, "audiopll_fracck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 					      "mainck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	hw = at91_clk_register_audio_pll_pad(regmap, "audiopll_padck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 					     "audiopll_fracck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	hw = at91_clk_register_audio_pll_pmc(regmap, "audiopll_pmcck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 					     "audiopll_fracck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	sama5d2_pmc->chws[PMC_AUDIOPLLCK] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	if (IS_ERR(regmap_sfr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		regmap_sfr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	hw = at91_clk_register_utmi(regmap, regmap_sfr, "utmick", "mainck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	sama5d2_pmc->chws[PMC_UTMI] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	parent_names[0] = slck_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	parent_names[1] = "mainck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	parent_names[2] = "plladivck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	parent_names[3] = "utmick";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 				      &at91sam9x5_master_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 				      &mck_characteristics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	sama5d2_pmc->chws[PMC_MCK] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	sama5d2_pmc->chws[PMC_MCK2] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	parent_names[0] = "plladivck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	parent_names[1] = "utmick";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	parent_names[0] = slck_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	parent_names[1] = "mainck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	parent_names[2] = "plladivck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	parent_names[3] = "utmick";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	parent_names[4] = "masterck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	parent_names[5] = "audiopll_pmcck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		char name[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		snprintf(name, sizeof(name), "prog%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		hw = at91_clk_register_programmable(regmap, name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 						    parent_names, 6, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 						    &sama5d2_programmable_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 						    NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		sama5d2_pmc->pchws[i] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	for (i = 0; i < ARRAY_SIZE(sama5d2_systemck); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		hw = at91_clk_register_system(regmap, sama5d2_systemck[i].n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 					      sama5d2_systemck[i].p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 					      sama5d2_systemck[i].id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 			goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		sama5d2_pmc->shws[sama5d2_systemck[i].id] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	for (i = 0; i < ARRAY_SIZE(sama5d2_periphck); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 							 &sama5d2_pcr_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 							 sama5d2_periphck[i].n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 							 "masterck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 							 sama5d2_periphck[i].id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 							 &range, INT_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 			goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		sama5d2_pmc->phws[sama5d2_periphck[i].id] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	for (i = 0; i < ARRAY_SIZE(sama5d2_periph32ck); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 							 &sama5d2_pcr_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 							 sama5d2_periph32ck[i].n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 							 "h32mxck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 							 sama5d2_periph32ck[i].id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 							 &sama5d2_periph32ck[i].r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 							 INT_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 			goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		sama5d2_pmc->phws[sama5d2_periph32ck[i].id] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	parent_names[0] = slck_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	parent_names[1] = "mainck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	parent_names[2] = "plladivck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	parent_names[3] = "utmick";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	parent_names[4] = "masterck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	parent_names[5] = "audiopll_pmcck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	for (i = 0; i < ARRAY_SIZE(sama5d2_gck); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 						 &sama5d2_pcr_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 						 sama5d2_gck[i].n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 						 parent_names, NULL, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 						 sama5d2_gck[i].id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 						 &sama5d2_gck[i].r,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 						 sama5d2_gck[i].chg_pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 			goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		sama5d2_pmc->ghws[sama5d2_gck[i].id] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	if (regmap_sfr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		parent_names[0] = "i2s0_clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		parent_names[1] = "i2s0_gclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		hw = at91_clk_i2s_mux_register(regmap_sfr, "i2s0_muxclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 					       parent_names, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 			goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		sama5d2_pmc->chws[PMC_I2S0_MUX] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		parent_names[0] = "i2s1_clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		parent_names[1] = "i2s1_gclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		hw = at91_clk_i2s_mux_register(regmap_sfr, "i2s1_muxclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 					       parent_names, 2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 			goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		sama5d2_pmc->chws[PMC_I2S1_MUX] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama5d2_pmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) err_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	kfree(sama5d2_pmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) CLK_OF_DECLARE_DRIVER(sama5d2_pmc, "atmel,sama5d2-pmc", sama5d2_pmc_setup);