Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <dt-bindings/clock/at91.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include "pmc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) static DEFINE_SPINLOCK(pmc_pll_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) static const struct clk_master_characteristics mck_characteristics = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 	.output = { .min = 140000000, .max = 200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 	.divisors = { 1, 2, 4, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 	.have_div3_pres = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) static const struct clk_master_layout sam9x60_master_layout = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	.mask = 0x373,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	.pres_shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	.offset = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) static const struct clk_range plla_outputs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	{ .min = 2343750, .max = 1200000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) static const struct clk_pll_characteristics plla_characteristics = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	.input = { .min = 12000000, .max = 48000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	.num_output = ARRAY_SIZE(plla_outputs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	.output = plla_outputs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) static const struct clk_range upll_outputs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	{ .min = 300000000, .max = 500000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static const struct clk_pll_characteristics upll_characteristics = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	.input = { .min = 12000000, .max = 48000000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	.num_output = ARRAY_SIZE(upll_outputs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	.output = upll_outputs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	.upll = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static const struct clk_pll_layout pll_frac_layout = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	.mul_mask = GENMASK(31, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	.frac_mask = GENMASK(21, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	.mul_shift = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	.frac_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static const struct clk_pll_layout pll_div_layout = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	.div_mask = GENMASK(7, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	.endiv_mask = BIT(29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	.div_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	.endiv_shift = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static const struct clk_programmable_layout sam9x60_programmable_layout = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	.pres_mask = 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	.pres_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	.css_mask = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	.have_slck_mck = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	.is_pres_direct = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static const struct clk_pcr_layout sam9x60_pcr_layout = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	.offset = 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	.cmd = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	.gckcss_mask = GENMASK(12, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	.pid_mask = GENMASK(6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	char *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	char *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) } sam9x60_systemck[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	{ .n = "ddrck",  .p = "masterck", .id = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	{ .n = "uhpck",  .p = "usbck",    .id = 6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	{ .n = "pck0",   .p = "prog0",    .id = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	{ .n = "pck1",   .p = "prog1",    .id = 9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	{ .n = "qspick", .p = "masterck", .id = 19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	char *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) } sam9x60_periphck[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	{ .n = "pioA_clk",   .id = 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	{ .n = "pioB_clk",   .id = 3, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	{ .n = "pioC_clk",   .id = 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	{ .n = "flex0_clk",  .id = 5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	{ .n = "flex1_clk",  .id = 6, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	{ .n = "flex2_clk",  .id = 7, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	{ .n = "flex3_clk",  .id = 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	{ .n = "flex6_clk",  .id = 9, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	{ .n = "flex7_clk",  .id = 10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	{ .n = "flex8_clk",  .id = 11, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	{ .n = "sdmmc0_clk", .id = 12, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	{ .n = "flex4_clk",  .id = 13, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	{ .n = "flex5_clk",  .id = 14, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	{ .n = "flex9_clk",  .id = 15, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	{ .n = "flex10_clk", .id = 16, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	{ .n = "tcb0_clk",   .id = 17, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	{ .n = "pwm_clk",    .id = 18, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	{ .n = "adc_clk",    .id = 19, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	{ .n = "dma0_clk",   .id = 20, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	{ .n = "matrix_clk", .id = 21, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	{ .n = "uhphs_clk",  .id = 22, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	{ .n = "udphs_clk",  .id = 23, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	{ .n = "macb0_clk",  .id = 24, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	{ .n = "lcd_clk",    .id = 25, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	{ .n = "sdmmc1_clk", .id = 26, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	{ .n = "macb1_clk",  .id = 27, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	{ .n = "ssc_clk",    .id = 28, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	{ .n = "can0_clk",   .id = 29, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	{ .n = "can1_clk",   .id = 30, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	{ .n = "flex11_clk", .id = 32, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	{ .n = "flex12_clk", .id = 33, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	{ .n = "i2s_clk",    .id = 34, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	{ .n = "qspi_clk",   .id = 35, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	{ .n = "gfx2d_clk",  .id = 36, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	{ .n = "pit64b_clk", .id = 37, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	{ .n = "trng_clk",   .id = 38, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	{ .n = "aes_clk",    .id = 39, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	{ .n = "tdes_clk",   .id = 40, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	{ .n = "sha_clk",    .id = 41, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	{ .n = "classd_clk", .id = 42, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	{ .n = "isi_clk",    .id = 43, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	{ .n = "pioD_clk",   .id = 44, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	{ .n = "tcb1_clk",   .id = 45, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	{ .n = "dbgu_clk",   .id = 47, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	{ .n = "mpddr_clk",  .id = 49, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	char *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	struct clk_range r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) } sam9x60_gck[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	{ .n = "flex0_gclk",  .id = 5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	{ .n = "flex1_gclk",  .id = 6, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	{ .n = "flex2_gclk",  .id = 7, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	{ .n = "flex3_gclk",  .id = 8, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	{ .n = "flex6_gclk",  .id = 9, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	{ .n = "flex7_gclk",  .id = 10, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	{ .n = "flex8_gclk",  .id = 11, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	{ .n = "sdmmc0_gclk", .id = 12, .r = { .min = 0, .max = 105000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	{ .n = "flex4_gclk",  .id = 13, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	{ .n = "flex5_gclk",  .id = 14, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	{ .n = "flex9_gclk",  .id = 15, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	{ .n = "flex10_gclk", .id = 16, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	{ .n = "tcb0_gclk",   .id = 17, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	{ .n = "adc_gclk",    .id = 19, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	{ .n = "lcd_gclk",    .id = 25, .r = { .min = 0, .max = 140000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	{ .n = "sdmmc1_gclk", .id = 26, .r = { .min = 0, .max = 105000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	{ .n = "flex11_gclk", .id = 32, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	{ .n = "flex12_gclk", .id = 33, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	{ .n = "i2s_gclk",    .id = 34, .r = { .min = 0, .max = 105000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	{ .n = "pit64b_gclk", .id = 37, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	{ .n = "classd_gclk", .id = 42, .r = { .min = 0, .max = 100000000 }, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	{ .n = "tcb1_gclk",   .id = 45, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	{ .n = "dbgu_gclk",   .id = 47, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static void __init sam9x60_pmc_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	struct clk_range range = CLK_RANGE(0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	const char *td_slck_name, *md_slck_name, *mainxtal_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	struct pmc_data *sam9x60_pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	const char *parent_names[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct clk_hw *main_osc_hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	i = of_property_match_string(np, "clock-names", "td_slck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	td_slck_name = of_clk_get_parent_name(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	i = of_property_match_string(np, "clock-names", "md_slck");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	md_slck_name = of_clk_get_parent_name(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	i = of_property_match_string(np, "clock-names", "main_xtal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	mainxtal_name = of_clk_get_parent_name(np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	regmap = device_node_to_regmap(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	sam9x60_pmc = pmc_data_allocate(PMC_PLLACK + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 					nck(sam9x60_systemck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 					nck(sam9x60_periphck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 					nck(sam9x60_gck), 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	if (!sam9x60_pmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 					   50000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	main_osc_hw = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	parent_names[0] = "main_rc_osc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	parent_names[1] = "main_osc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	sam9x60_pmc->chws[PMC_MAIN] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "pllack_fracck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 					   "mainck", sam9x60_pmc->chws[PMC_MAIN],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 					   0, &plla_characteristics,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 					   &pll_frac_layout, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "pllack_divck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 					  "pllack_fracck", 0, &plla_characteristics,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 					  &pll_div_layout, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	sam9x60_pmc->chws[PMC_PLLACK] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	hw = sam9x60_clk_register_frac_pll(regmap, &pmc_pll_lock, "upllck_fracck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 					   "main_osc", main_osc_hw, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 					   &upll_characteristics,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 					   &pll_frac_layout, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	hw = sam9x60_clk_register_div_pll(regmap, &pmc_pll_lock, "upllck_divck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 					  "upllck_fracck", 1, &upll_characteristics,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 					  &pll_div_layout, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	sam9x60_pmc->chws[PMC_UTMI] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	parent_names[0] = md_slck_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	parent_names[1] = "mainck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	parent_names[2] = "pllack_divck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	hw = at91_clk_register_master(regmap, "masterck", 3, parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 				      &sam9x60_master_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 				      &mck_characteristics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	sam9x60_pmc->chws[PMC_MCK] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	parent_names[0] = "pllack_divck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	parent_names[1] = "upllck_divck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	parent_names[2] = "main_osc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	hw = sam9x60_clk_register_usb(regmap, "usbck", parent_names, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	parent_names[0] = md_slck_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	parent_names[1] = td_slck_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	parent_names[2] = "mainck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	parent_names[3] = "masterck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	parent_names[4] = "pllack_divck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	parent_names[5] = "upllck_divck";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	for (i = 0; i < 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		char name[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		snprintf(name, sizeof(name), "prog%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		hw = at91_clk_register_programmable(regmap, name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 						    parent_names, 6, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 						    &sam9x60_programmable_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 						    NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 			goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		sam9x60_pmc->pchws[i] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	for (i = 0; i < ARRAY_SIZE(sam9x60_systemck); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		hw = at91_clk_register_system(regmap, sam9x60_systemck[i].n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 					      sam9x60_systemck[i].p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 					      sam9x60_systemck[i].id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 			goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		sam9x60_pmc->shws[sam9x60_systemck[i].id] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	for (i = 0; i < ARRAY_SIZE(sam9x60_periphck); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 							 &sam9x60_pcr_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 							 sam9x60_periphck[i].n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 							 "masterck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 							 sam9x60_periphck[i].id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 							 &range, INT_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 			goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		sam9x60_pmc->phws[sam9x60_periphck[i].id] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	for (i = 0; i < ARRAY_SIZE(sam9x60_gck); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 						 &sam9x60_pcr_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 						 sam9x60_gck[i].n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 						 parent_names, NULL, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 						 sam9x60_gck[i].id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 						 &sam9x60_gck[i].r, INT_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 			goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		sam9x60_pmc->ghws[sam9x60_gck[i].id] = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sam9x60_pmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) err_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	kfree(sam9x60_pmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* Some clks are used for a clocksource */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) CLK_OF_DECLARE(sam9x60_pmc, "microchip,sam9x60-pmc", sam9x60_pmc_setup);