Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * drivers/clk/at91/pmc.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #ifndef __PMC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define __PMC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) extern spinlock_t pmc_pcr_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) struct pmc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	unsigned int ncore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	struct clk_hw **chws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	unsigned int nsystem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	struct clk_hw **shws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	unsigned int nperiph;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	struct clk_hw **phws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	unsigned int ngck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	struct clk_hw **ghws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	unsigned int npck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	struct clk_hw **pchws;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	struct clk_hw *hwtable[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) struct clk_range {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	unsigned long min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	unsigned long max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define CLK_RANGE(MIN, MAX) {.min = MIN, .max = MAX,}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) struct clk_master_layout {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	u8 pres_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) extern const struct clk_master_layout at91rm9200_master_layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) extern const struct clk_master_layout at91sam9x5_master_layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) struct clk_master_characteristics {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	struct clk_range output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	u32 divisors[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	u8 have_div3_pres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) struct clk_pll_layout {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	u32 pllr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u32 mul_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	u32 frac_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	u32 div_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	u32 endiv_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	u8 mul_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	u8 frac_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	u8 div_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	u8 endiv_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) extern const struct clk_pll_layout at91rm9200_pll_layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) extern const struct clk_pll_layout at91sam9g45_pll_layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) extern const struct clk_pll_layout at91sam9g20_pllb_layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) extern const struct clk_pll_layout sama5d3_pll_layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) struct clk_pll_characteristics {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	struct clk_range input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	int num_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	const struct clk_range *output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u16 *icpll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	u8 *out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	u8 upll : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) struct clk_programmable_layout {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	u8 pres_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	u8 pres_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	u8 css_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	u8 have_slck_mck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	u8 is_pres_direct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) extern const struct clk_programmable_layout at91rm9200_programmable_layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) extern const struct clk_programmable_layout at91sam9g45_programmable_layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) extern const struct clk_programmable_layout at91sam9x5_programmable_layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) struct clk_pcr_layout {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	u32 div_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	u32 gckcss_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	u32 pid_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ndck(a, s) (a[s - 1].id + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define nck(a) (a[ARRAY_SIZE(a) - 1].id + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 				   unsigned int nperiph, unsigned int ngck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 				   unsigned int npck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int of_at91_get_clk_range(struct device_node *np, const char *propname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			  struct clk_range *range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct clk_hw *of_clk_hw_pmc_get(struct of_phandle_args *clkspec, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) at91_clk_register_audio_pll_frac(struct regmap *regmap, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 				 const char *parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 				const char *parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 				const char *parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			    const struct clk_pcr_layout *layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			    const char *name, const char **parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			    u32 *mux_table, u8 num_parents, u8 id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			    const struct clk_range *range, int chg_pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) at91_clk_register_h32mx(struct regmap *regmap, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 			const char *parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) at91_clk_i2s_mux_register(struct regmap *regmap, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			  const char * const *parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			  unsigned int num_parents, u8 bus_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) at91_clk_register_main_rc_osc(struct regmap *regmap, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			      u32 frequency, u32 accuracy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) at91_clk_register_main_osc(struct regmap *regmap, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			   const char *parent_name, bool bypass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) at91_clk_register_rm9200_main(struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			      const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			      const char *parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) at91_clk_register_sam9x5_main(struct regmap *regmap, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			      const char **parent_names, int num_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) at91_clk_register_master(struct regmap *regmap, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			 int num_parents, const char **parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			 const struct clk_master_layout *layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			 const struct clk_master_characteristics *characteristics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) at91_clk_sama7g5_register_master(struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 				 const char *name, int num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 				 const char **parent_names, u32 *mux_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 				 spinlock_t *lock, u8 id, bool critical,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 				 int chg_pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) at91_clk_register_peripheral(struct regmap *regmap, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			     const char *parent_name, u32 id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 				    const struct clk_pcr_layout *layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 				    const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 				    u32 id, const struct clk_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 				    int chg_pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) at91_clk_register_pll(struct regmap *regmap, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		      const char *parent_name, u8 id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		      const struct clk_pll_layout *layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		      const struct clk_pll_characteristics *characteristics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) at91_clk_register_plldiv(struct regmap *regmap, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			 const char *parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			     const char *name, const char *parent_name, u8 id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			     const struct clk_pll_characteristics *characteristics,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			     const struct clk_pll_layout *layout, bool critical);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			      const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			      struct clk_hw *parent_hw, u8 id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			      const struct clk_pll_characteristics *characteristics,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			      const struct clk_pll_layout *layout, bool critical);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) at91_clk_register_programmable(struct regmap *regmap, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			       const char **parent_names, u8 num_parents, u8 id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 			       const struct clk_programmable_layout *layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			       u32 *mux_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) at91_clk_register_sam9260_slow(struct regmap *regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			       const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			       const char **parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			       int num_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			    const char **parent_names, u8 num_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) at91_clk_register_system(struct regmap *regmap, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 			 const char *parent_name, u8 id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			    const char **parent_names, u8 num_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) at91sam9n12_clk_register_usb(struct regmap *regmap, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 			     const char *parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) sam9x60_clk_register_usb(struct regmap *regmap, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			 const char **parent_names, u8 num_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) at91rm9200_clk_register_usb(struct regmap *regmap, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			    const char *parent_name, const u32 *divisors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		       const char *name, const char *parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) at91_clk_sama7g5_register_utmi(struct regmap *regmap, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			       const char *parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) void pmc_register_id(u8 id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) void pmc_register_pck(u8 pck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static inline void pmc_register_id(u8 id) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static inline void pmc_register_pck(u8 pck) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #endif /* __PMC_H_ */