Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *  Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk/at91_pmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/proc-fns.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <dt-bindings/clock/at91.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "pmc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define PMC_MAX_IDS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define PMC_MAX_PCKS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) int of_at91_get_clk_range(struct device_node *np, const char *propname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 			  struct clk_range *range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	u32 min, max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	ret = of_property_read_u32_index(np, propname, 0, &min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	ret = of_property_read_u32_index(np, propname, 1, &max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	if (range) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		range->min = min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		range->max = max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) EXPORT_SYMBOL_GPL(of_at91_get_clk_range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) struct clk_hw *of_clk_hw_pmc_get(struct of_phandle_args *clkspec, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	unsigned int type = clkspec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	unsigned int idx = clkspec->args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct pmc_data *pmc_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	case PMC_TYPE_CORE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		if (idx < pmc_data->ncore)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 			return pmc_data->chws[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	case PMC_TYPE_SYSTEM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		if (idx < pmc_data->nsystem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 			return pmc_data->shws[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	case PMC_TYPE_PERIPHERAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		if (idx < pmc_data->nperiph)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 			return pmc_data->phws[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	case PMC_TYPE_GCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		if (idx < pmc_data->ngck)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 			return pmc_data->ghws[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	case PMC_TYPE_PROGRAMMABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		if (idx < pmc_data->npck)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 			return pmc_data->pchws[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	pr_err("%s: invalid type (%u) or index (%u)\n", __func__, type, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 				   unsigned int nperiph, unsigned int ngck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 				   unsigned int npck)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	unsigned int num_clks = ncore + nsystem + nperiph + ngck + npck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct pmc_data *pmc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	pmc_data = kzalloc(struct_size(pmc_data, hwtable, num_clks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 			   GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	if (!pmc_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	pmc_data->ncore = ncore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	pmc_data->chws = pmc_data->hwtable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	pmc_data->nsystem = nsystem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	pmc_data->shws = pmc_data->chws + ncore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	pmc_data->nperiph = nperiph;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	pmc_data->phws = pmc_data->shws + nsystem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	pmc_data->ngck = ngck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	pmc_data->ghws = pmc_data->phws + nperiph;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	pmc_data->npck = npck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	pmc_data->pchws = pmc_data->ghws + ngck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	return pmc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static struct regmap *pmcreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static u8 registered_ids[PMC_MAX_IDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static u8 registered_pcks[PMC_MAX_PCKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	u32 scsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	u32 pcsr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	u32 uckr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	u32 mor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	u32 mcfr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	u32 pllar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	u32 mckr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	u32 usb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	u32 imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	u32 pcsr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	u32 pcr[PMC_MAX_IDS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	u32 audio_pll0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	u32 audio_pll1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	u32 pckr[PMC_MAX_PCKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) } pmc_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)  * As Peripheral ID 0 is invalid on AT91 chips, the identifier is stored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)  * without alteration in the table, and 0 is for unused clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) void pmc_register_id(u8 id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	for (i = 0; i < PMC_MAX_IDS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		if (registered_ids[i] == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			registered_ids[i] = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		if (registered_ids[i] == id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)  * As Programmable Clock 0 is valid on AT91 chips, there is an offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  * of 1 between the stored value and the real clock ID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) void pmc_register_pck(u8 pck)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	for (i = 0; i < PMC_MAX_PCKS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		if (registered_pcks[i] == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			registered_pcks[i] = pck + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		if (registered_pcks[i] == (pck + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int pmc_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	u8 num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	regmap_read(pmcreg, AT91_PMC_SCSR, &pmc_cache.scsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	regmap_read(pmcreg, AT91_PMC_PCSR, &pmc_cache.pcsr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	regmap_read(pmcreg, AT91_CKGR_UCKR, &pmc_cache.uckr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	regmap_read(pmcreg, AT91_CKGR_MOR, &pmc_cache.mor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	regmap_read(pmcreg, AT91_CKGR_MCFR, &pmc_cache.mcfr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	regmap_read(pmcreg, AT91_CKGR_PLLAR, &pmc_cache.pllar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	regmap_read(pmcreg, AT91_PMC_MCKR, &pmc_cache.mckr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	regmap_read(pmcreg, AT91_PMC_USB, &pmc_cache.usb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	regmap_read(pmcreg, AT91_PMC_IMR, &pmc_cache.imr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	regmap_read(pmcreg, AT91_PMC_PCSR1, &pmc_cache.pcsr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	for (i = 0; registered_ids[i]; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		regmap_write(pmcreg, AT91_PMC_PCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			     (registered_ids[i] & AT91_PMC_PCR_PID_MASK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		regmap_read(pmcreg, AT91_PMC_PCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			    &pmc_cache.pcr[registered_ids[i]]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	for (i = 0; registered_pcks[i]; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		num = registered_pcks[i] - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		regmap_read(pmcreg, AT91_PMC_PCKR(num), &pmc_cache.pckr[num]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static bool pmc_ready(unsigned int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	regmap_read(pmcreg, AT91_PMC_SR, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	return ((status & mask) == mask) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static void pmc_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	u8 num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	u32 mask = AT91_PMC_MCKRDY | AT91_PMC_LOCKA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	regmap_read(pmcreg, AT91_PMC_MCKR, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	if (pmc_cache.mckr != tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		pr_warn("MCKR was not configured properly by the firmware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	regmap_read(pmcreg, AT91_CKGR_PLLAR, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	if (pmc_cache.pllar != tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		pr_warn("PLLAR was not configured properly by the firmware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	regmap_write(pmcreg, AT91_PMC_SCER, pmc_cache.scsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	regmap_write(pmcreg, AT91_PMC_PCER, pmc_cache.pcsr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	regmap_write(pmcreg, AT91_CKGR_UCKR, pmc_cache.uckr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	regmap_write(pmcreg, AT91_CKGR_MOR, pmc_cache.mor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	regmap_write(pmcreg, AT91_CKGR_MCFR, pmc_cache.mcfr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	regmap_write(pmcreg, AT91_PMC_USB, pmc_cache.usb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	regmap_write(pmcreg, AT91_PMC_IMR, pmc_cache.imr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	regmap_write(pmcreg, AT91_PMC_PCER1, pmc_cache.pcsr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	for (i = 0; registered_ids[i]; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		regmap_write(pmcreg, AT91_PMC_PCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			     pmc_cache.pcr[registered_ids[i]] |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			     AT91_PMC_PCR_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	for (i = 0; registered_pcks[i]; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		num = registered_pcks[i] - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		regmap_write(pmcreg, AT91_PMC_PCKR(num), pmc_cache.pckr[num]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (pmc_cache.uckr & AT91_PMC_UPLLEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		mask |= AT91_PMC_LOCKU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	while (!pmc_ready(mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static struct syscore_ops pmc_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	.suspend = pmc_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	.resume = pmc_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static const struct of_device_id sama5d2_pmc_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	{ .compatible = "atmel,sama5d2-pmc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static int __init pmc_register_ops(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	np = of_find_matching_node(NULL, sama5d2_pmc_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	if (!of_device_is_available(np)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	pmcreg = device_node_to_regmap(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	if (IS_ERR(pmcreg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		return PTR_ERR(pmcreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	register_syscore_ops(&pmc_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* This has to happen before arch_initcall because of the tcb_clksrc driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) postcore_initcall(pmc_register_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #endif