^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/clk/at91_pmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "pmc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define MASTER_SOURCE_MAX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PERIPHERAL_AT91RM9200 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PERIPHERAL_AT91SAM9X5 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PERIPHERAL_MAX 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PERIPHERAL_ID_MIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PROG_SOURCE_MAX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PROG_ID_MAX 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SYSTEM_MAX_ID 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define GCK_INDEX_DT_AUDIO_PLL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #ifdef CONFIG_HAVE_AT91_AUDIO_PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static void __init of_sama5d2_clk_audio_pll_frac_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) const char *name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) regmap = syscon_node_to_regmap(of_get_parent(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) parent_name = of_clk_get_parent_name(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) hw = at91_clk_register_audio_pll_frac(regmap, name, parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_frac_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "atmel,sama5d2-clk-audio-pll-frac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) of_sama5d2_clk_audio_pll_frac_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static void __init of_sama5d2_clk_audio_pll_pad_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) const char *name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) regmap = syscon_node_to_regmap(of_get_parent(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) parent_name = of_clk_get_parent_name(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) hw = at91_clk_register_audio_pll_pad(regmap, name, parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pad_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) "atmel,sama5d2-clk-audio-pll-pad",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) of_sama5d2_clk_audio_pll_pad_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static void __init of_sama5d2_clk_audio_pll_pmc_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) const char *name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) regmap = syscon_node_to_regmap(of_get_parent(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) parent_name = of_clk_get_parent_name(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) hw = at91_clk_register_audio_pll_pmc(regmap, name, parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) CLK_OF_DECLARE(of_sama5d2_clk_audio_pll_pmc_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) "atmel,sama5d2-clk-audio-pll-pmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) of_sama5d2_clk_audio_pll_pmc_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #endif /* CONFIG_HAVE_AT91_AUDIO_PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static const struct clk_pcr_layout dt_pcr_layout = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .offset = 0x10c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .cmd = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .pid_mask = GENMASK(5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .div_mask = GENMASK(17, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .gckcss_mask = GENMASK(10, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #ifdef CONFIG_HAVE_AT91_GENERATED_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define GENERATED_SOURCE_MAX 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define GCK_ID_I2S0 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define GCK_ID_I2S1 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define GCK_ID_CLASSD 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned int num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) const char *parent_names[GENERATED_SOURCE_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct device_node *gcknp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct clk_range range = CLK_RANGE(0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) num_parents = of_clk_get_parent_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (num_parents == 0 || num_parents > GENERATED_SOURCE_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) of_clk_parent_fill(np, parent_names, num_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) num = of_get_child_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (!num || num > PERIPHERAL_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) regmap = syscon_node_to_regmap(of_get_parent(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) for_each_child_of_node(np, gcknp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int chg_pid = INT_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (of_property_read_u32(gcknp, "reg", &id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (id < PERIPHERAL_ID_MIN || id >= PERIPHERAL_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (of_property_read_string(np, "clock-output-names", &name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) name = gcknp->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) of_at91_get_clk_range(gcknp, "atmel,clk-output-range",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) &range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (of_device_is_compatible(np, "atmel,sama5d2-clk-generated") &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) (id == GCK_ID_I2S0 || id == GCK_ID_I2S1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) id == GCK_ID_CLASSD))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) chg_pid = GCK_INDEX_DT_AUDIO_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) &dt_pcr_layout, name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) parent_names, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) num_parents, id, &range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) chg_pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) of_clk_add_hw_provider(gcknp, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) CLK_OF_DECLARE(of_sama5d2_clk_generated_setup, "atmel,sama5d2-clk-generated",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) of_sama5d2_clk_generated_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #endif /* CONFIG_HAVE_AT91_GENERATED_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #ifdef CONFIG_HAVE_AT91_H32MX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void __init of_sama5d4_clk_h32mx_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) const char *name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) regmap = syscon_node_to_regmap(of_get_parent(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) parent_name = of_clk_get_parent_name(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) hw = at91_clk_register_h32mx(regmap, name, parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) CLK_OF_DECLARE(of_sama5d4_clk_h32mx_setup, "atmel,sama5d4-clk-h32mx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) of_sama5d4_clk_h32mx_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #endif /* CONFIG_HAVE_AT91_H32MX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #ifdef CONFIG_HAVE_AT91_I2S_MUX_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define I2S_BUS_NR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static void __init of_sama5d2_clk_i2s_mux_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct regmap *regmap_sfr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u8 bus_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) const char *parent_names[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct device_node *i2s_mux_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (IS_ERR(regmap_sfr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) for_each_child_of_node(np, i2s_mux_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (of_property_read_u8(i2s_mux_np, "reg", &bus_id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (bus_id > I2S_BUS_NR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret = of_clk_parent_fill(i2s_mux_np, parent_names, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (ret != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) hw = at91_clk_i2s_mux_register(regmap_sfr, i2s_mux_np->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) parent_names, 2, bus_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) of_clk_add_hw_provider(i2s_mux_np, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) CLK_OF_DECLARE(sama5d2_clk_i2s_mux, "atmel,sama5d2-clk-i2s-mux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) of_sama5d2_clk_i2s_mux_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #endif /* CONFIG_HAVE_AT91_I2S_MUX_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) const char *name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) bool bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) of_property_read_string(np, "clock-output-names", &name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) bypass = of_property_read_bool(np, "atmel,osc-bypass");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) parent_name = of_clk_get_parent_name(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) regmap = syscon_node_to_regmap(of_get_parent(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) hw = at91_clk_register_main_osc(regmap, name, parent_name, bypass);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) CLK_OF_DECLARE(at91rm9200_clk_main_osc, "atmel,at91rm9200-clk-main-osc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) of_at91rm9200_clk_main_osc_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static void __init of_at91sam9x5_clk_main_rc_osc_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u32 frequency = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 accuracy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) const char *name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) of_property_read_string(np, "clock-output-names", &name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) of_property_read_u32(np, "clock-frequency", &frequency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) of_property_read_u32(np, "clock-accuracy", &accuracy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) regmap = syscon_node_to_regmap(of_get_parent(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) hw = at91_clk_register_main_rc_osc(regmap, name, frequency, accuracy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) CLK_OF_DECLARE(at91sam9x5_clk_main_rc_osc, "atmel,at91sam9x5-clk-main-rc-osc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) of_at91sam9x5_clk_main_rc_osc_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static void __init of_at91rm9200_clk_main_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) const char *name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) parent_name = of_clk_get_parent_name(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) of_property_read_string(np, "clock-output-names", &name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) regmap = syscon_node_to_regmap(of_get_parent(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) hw = at91_clk_register_rm9200_main(regmap, name, parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) CLK_OF_DECLARE(at91rm9200_clk_main, "atmel,at91rm9200-clk-main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) of_at91rm9200_clk_main_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static void __init of_at91sam9x5_clk_main_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) const char *parent_names[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) unsigned int num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) const char *name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) num_parents = of_clk_get_parent_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (num_parents == 0 || num_parents > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) of_clk_parent_fill(np, parent_names, num_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) regmap = syscon_node_to_regmap(of_get_parent(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) of_property_read_string(np, "clock-output-names", &name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) hw = at91_clk_register_sam9x5_main(regmap, name, parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) num_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) CLK_OF_DECLARE(at91sam9x5_clk_main, "atmel,at91sam9x5-clk-main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) of_at91sam9x5_clk_main_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static struct clk_master_characteristics * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) of_at91_clk_master_get_characteristics(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct clk_master_characteristics *characteristics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (!characteristics)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (of_at91_get_clk_range(np, "atmel,clk-output-range", &characteristics->output))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) goto out_free_characteristics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) of_property_read_u32_array(np, "atmel,clk-divisors",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) characteristics->divisors, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) characteristics->have_div3_pres =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) of_property_read_bool(np, "atmel,master-clk-have-div3-pres");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return characteristics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) out_free_characteristics:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) kfree(characteristics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) of_at91_clk_master_setup(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) const struct clk_master_layout *layout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) unsigned int num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) const char *parent_names[MASTER_SOURCE_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) const char *name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct clk_master_characteristics *characteristics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) num_parents = of_clk_get_parent_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (num_parents == 0 || num_parents > MASTER_SOURCE_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) of_clk_parent_fill(np, parent_names, num_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) of_property_read_string(np, "clock-output-names", &name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) characteristics = of_at91_clk_master_get_characteristics(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (!characteristics)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) regmap = syscon_node_to_regmap(of_get_parent(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) hw = at91_clk_register_master(regmap, name, num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) parent_names, layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) characteristics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) goto out_free_characteristics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) out_free_characteristics:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) kfree(characteristics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static void __init of_at91rm9200_clk_master_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) of_at91_clk_master_setup(np, &at91rm9200_master_layout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) CLK_OF_DECLARE(at91rm9200_clk_master, "atmel,at91rm9200-clk-master",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) of_at91rm9200_clk_master_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static void __init of_at91sam9x5_clk_master_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) of_at91_clk_master_setup(np, &at91sam9x5_master_layout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) CLK_OF_DECLARE(at91sam9x5_clk_master, "atmel,at91sam9x5-clk-master",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) of_at91sam9x5_clk_master_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) of_at91_clk_periph_setup(struct device_node *np, u8 type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct device_node *periphclknp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) parent_name = of_clk_get_parent_name(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (!parent_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) num = of_get_child_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (!num || num > PERIPHERAL_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) regmap = syscon_node_to_regmap(of_get_parent(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) for_each_child_of_node(np, periphclknp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (of_property_read_u32(periphclknp, "reg", &id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (id >= PERIPHERAL_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (of_property_read_string(np, "clock-output-names", &name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) name = periphclknp->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (type == PERIPHERAL_AT91RM9200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) hw = at91_clk_register_peripheral(regmap, name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) parent_name, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct clk_range range = CLK_RANGE(0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) of_at91_get_clk_range(periphclknp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) "atmel,clk-output-range",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) &range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) hw = at91_clk_register_sam9x5_peripheral(regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) &pmc_pcr_lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) &dt_pcr_layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) id, &range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) INT_MIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) of_clk_add_hw_provider(periphclknp, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static void __init of_at91rm9200_clk_periph_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) of_at91_clk_periph_setup(np, PERIPHERAL_AT91RM9200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) CLK_OF_DECLARE(at91rm9200_clk_periph, "atmel,at91rm9200-clk-peripheral",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) of_at91rm9200_clk_periph_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static void __init of_at91sam9x5_clk_periph_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) of_at91_clk_periph_setup(np, PERIPHERAL_AT91SAM9X5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) CLK_OF_DECLARE(at91sam9x5_clk_periph, "atmel,at91sam9x5-clk-peripheral",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) of_at91sam9x5_clk_periph_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static struct clk_pll_characteristics * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) of_at91_clk_pll_get_characteristics(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) int num_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) u32 num_cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct clk_range input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct clk_range *output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) u8 *out = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u16 *icpll = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct clk_pll_characteristics *characteristics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (of_at91_get_clk_range(np, "atmel,clk-input-range", &input))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (of_property_read_u32(np, "#atmel,pll-clk-output-range-cells",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) &num_cells))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (num_cells < 2 || num_cells > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (!of_get_property(np, "atmel,pll-clk-output-ranges", &tmp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) num_output = tmp / (sizeof(u32) * num_cells);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (!characteristics)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) output = kcalloc(num_output, sizeof(*output), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (!output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) goto out_free_characteristics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (num_cells > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) out = kcalloc(num_output, sizeof(*out), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (!out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) goto out_free_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (num_cells > 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) icpll = kcalloc(num_output, sizeof(*icpll), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (!icpll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) goto out_free_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) for (i = 0; i < num_output; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) offset = i * num_cells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (of_property_read_u32_index(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) "atmel,pll-clk-output-ranges",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) offset, &tmp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) goto out_free_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) output[i].min = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (of_property_read_u32_index(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) "atmel,pll-clk-output-ranges",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) offset + 1, &tmp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) goto out_free_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) output[i].max = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (num_cells == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (of_property_read_u32_index(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) "atmel,pll-clk-output-ranges",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) offset + 2, &tmp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) goto out_free_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) out[i] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (num_cells == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (of_property_read_u32_index(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) "atmel,pll-clk-output-ranges",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) offset + 3, &tmp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) goto out_free_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) icpll[i] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) characteristics->input = input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) characteristics->num_output = num_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) characteristics->output = output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) characteristics->out = out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) characteristics->icpll = icpll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return characteristics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) out_free_output:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) kfree(icpll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) kfree(out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) kfree(output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) out_free_characteristics:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) kfree(characteristics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) of_at91_clk_pll_setup(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) const struct clk_pll_layout *layout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) const char *name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct clk_pll_characteristics *characteristics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (of_property_read_u32(np, "reg", &id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) parent_name = of_clk_get_parent_name(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) of_property_read_string(np, "clock-output-names", &name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) regmap = syscon_node_to_regmap(of_get_parent(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) characteristics = of_at91_clk_pll_get_characteristics(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (!characteristics)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) hw = at91_clk_register_pll(regmap, name, parent_name, id, layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) characteristics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) goto out_free_characteristics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) out_free_characteristics:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) kfree(characteristics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static void __init of_at91rm9200_clk_pll_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) of_at91_clk_pll_setup(np, &at91rm9200_pll_layout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) CLK_OF_DECLARE(at91rm9200_clk_pll, "atmel,at91rm9200-clk-pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) of_at91rm9200_clk_pll_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static void __init of_at91sam9g45_clk_pll_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) of_at91_clk_pll_setup(np, &at91sam9g45_pll_layout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) CLK_OF_DECLARE(at91sam9g45_clk_pll, "atmel,at91sam9g45-clk-pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) of_at91sam9g45_clk_pll_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) of_at91_clk_pll_setup(np, &at91sam9g20_pllb_layout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) CLK_OF_DECLARE(at91sam9g20_clk_pllb, "atmel,at91sam9g20-clk-pllb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) of_at91sam9g20_clk_pllb_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static void __init of_sama5d3_clk_pll_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) of_at91_clk_pll_setup(np, &sama5d3_pll_layout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) CLK_OF_DECLARE(sama5d3_clk_pll, "atmel,sama5d3-clk-pll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) of_sama5d3_clk_pll_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) of_at91sam9x5_clk_plldiv_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) const char *name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) parent_name = of_clk_get_parent_name(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) of_property_read_string(np, "clock-output-names", &name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) regmap = syscon_node_to_regmap(of_get_parent(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) hw = at91_clk_register_plldiv(regmap, name, parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) CLK_OF_DECLARE(at91sam9x5_clk_plldiv, "atmel,at91sam9x5-clk-plldiv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) of_at91sam9x5_clk_plldiv_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) of_at91_clk_prog_setup(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) const struct clk_programmable_layout *layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) u32 *mux_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) unsigned int num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) const char *parent_names[PROG_SOURCE_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct device_node *progclknp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) num_parents = of_clk_get_parent_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (num_parents == 0 || num_parents > PROG_SOURCE_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) of_clk_parent_fill(np, parent_names, num_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) num = of_get_child_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (!num || num > (PROG_ID_MAX + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) regmap = syscon_node_to_regmap(of_get_parent(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) for_each_child_of_node(np, progclknp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (of_property_read_u32(progclknp, "reg", &id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (of_property_read_string(np, "clock-output-names", &name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) name = progclknp->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) hw = at91_clk_register_programmable(regmap, name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) parent_names, num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) id, layout, mux_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) of_clk_add_hw_provider(progclknp, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static void __init of_at91rm9200_clk_prog_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) of_at91_clk_prog_setup(np, &at91rm9200_programmable_layout, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) CLK_OF_DECLARE(at91rm9200_clk_prog, "atmel,at91rm9200-clk-programmable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) of_at91rm9200_clk_prog_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static void __init of_at91sam9g45_clk_prog_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) of_at91_clk_prog_setup(np, &at91sam9g45_programmable_layout, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) CLK_OF_DECLARE(at91sam9g45_clk_prog, "atmel,at91sam9g45-clk-programmable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) of_at91sam9g45_clk_prog_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static void __init of_at91sam9x5_clk_prog_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) of_at91_clk_prog_setup(np, &at91sam9x5_programmable_layout, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) CLK_OF_DECLARE(at91sam9x5_clk_prog, "atmel,at91sam9x5-clk-programmable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) of_at91sam9x5_clk_prog_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static void __init of_at91sam9260_clk_slow_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) const char *parent_names[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) unsigned int num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) const char *name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) num_parents = of_clk_get_parent_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (num_parents != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) of_clk_parent_fill(np, parent_names, num_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) regmap = syscon_node_to_regmap(of_get_parent(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) of_property_read_string(np, "clock-output-names", &name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) hw = at91_clk_register_sam9260_slow(regmap, name, parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) num_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) CLK_OF_DECLARE(at91sam9260_clk_slow, "atmel,at91sam9260-clk-slow",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) of_at91sam9260_clk_slow_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #ifdef CONFIG_HAVE_AT91_SMD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define SMD_SOURCE_MAX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static void __init of_at91sam9x5_clk_smd_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) unsigned int num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) const char *parent_names[SMD_SOURCE_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) const char *name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) num_parents = of_clk_get_parent_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (num_parents == 0 || num_parents > SMD_SOURCE_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) of_clk_parent_fill(np, parent_names, num_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) of_property_read_string(np, "clock-output-names", &name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) regmap = syscon_node_to_regmap(of_get_parent(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) hw = at91sam9x5_clk_register_smd(regmap, name, parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) num_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) CLK_OF_DECLARE(at91sam9x5_clk_smd, "atmel,at91sam9x5-clk-smd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) of_at91sam9x5_clk_smd_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #endif /* CONFIG_HAVE_AT91_SMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static void __init of_at91rm9200_clk_sys_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) struct device_node *sysclknp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) num = of_get_child_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (num > (SYSTEM_MAX_ID + 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) regmap = syscon_node_to_regmap(of_get_parent(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) for_each_child_of_node(np, sysclknp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (of_property_read_u32(sysclknp, "reg", &id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (of_property_read_string(np, "clock-output-names", &name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) name = sysclknp->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) parent_name = of_clk_get_parent_name(sysclknp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) hw = at91_clk_register_system(regmap, name, parent_name, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) of_clk_add_hw_provider(sysclknp, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) CLK_OF_DECLARE(at91rm9200_clk_sys, "atmel,at91rm9200-clk-system",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) of_at91rm9200_clk_sys_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #ifdef CONFIG_HAVE_AT91_USB_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define USB_SOURCE_MAX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static void __init of_at91sam9x5_clk_usb_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) unsigned int num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) const char *parent_names[USB_SOURCE_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) const char *name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) num_parents = of_clk_get_parent_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (num_parents == 0 || num_parents > USB_SOURCE_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) of_clk_parent_fill(np, parent_names, num_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) of_property_read_string(np, "clock-output-names", &name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) regmap = syscon_node_to_regmap(of_get_parent(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) hw = at91sam9x5_clk_register_usb(regmap, name, parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) num_parents);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) CLK_OF_DECLARE(at91sam9x5_clk_usb, "atmel,at91sam9x5-clk-usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) of_at91sam9x5_clk_usb_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) static void __init of_at91sam9n12_clk_usb_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) const char *name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) parent_name = of_clk_get_parent_name(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (!parent_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) of_property_read_string(np, "clock-output-names", &name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) regmap = syscon_node_to_regmap(of_get_parent(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) hw = at91sam9n12_clk_register_usb(regmap, name, parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) CLK_OF_DECLARE(at91sam9n12_clk_usb, "atmel,at91sam9n12-clk-usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) of_at91sam9n12_clk_usb_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static void __init of_at91rm9200_clk_usb_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) const char *name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) u32 divisors[4] = {0, 0, 0, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) parent_name = of_clk_get_parent_name(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (!parent_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) of_property_read_u32_array(np, "atmel,clk-divisors", divisors, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (!divisors[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) of_property_read_string(np, "clock-output-names", &name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) regmap = syscon_node_to_regmap(of_get_parent(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (IS_ERR(regmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) hw = at91rm9200_clk_register_usb(regmap, name, parent_name, divisors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) CLK_OF_DECLARE(at91rm9200_clk_usb, "atmel,at91rm9200-clk-usb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) of_at91rm9200_clk_usb_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #endif /* CONFIG_HAVE_AT91_USB_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #ifdef CONFIG_HAVE_AT91_UTMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) const char *parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) const char *name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) struct regmap *regmap_pmc, *regmap_sfr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) parent_name = of_clk_get_parent_name(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) of_property_read_string(np, "clock-output-names", &name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) regmap_pmc = syscon_node_to_regmap(of_get_parent(np));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (IS_ERR(regmap_pmc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * If the device supports different mainck rates, this value has to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) * set in the UTMI Clock Trimming register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) * - 9x5: mainck supports several rates but it is indicated that a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * 12 MHz is needed in case of USB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * - sama5d3 and sama5d2: mainck supports several rates. Configuring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) * the FREQ field of the UTMI Clock Trimming register is mandatory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) * - sama5d4: mainck is at 12 MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) * We only need to retrieve sama5d3 or sama5d2 sfr regmap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d3-sfr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (IS_ERR(regmap_sfr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (IS_ERR(regmap_sfr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) regmap_sfr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) hw = at91_clk_register_utmi(regmap_pmc, regmap_sfr, name, parent_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (IS_ERR(hw))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) CLK_OF_DECLARE(at91sam9x5_clk_utmi, "atmel,at91sam9x5-clk-utmi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) of_at91sam9x5_clk_utmi_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #endif /* CONFIG_HAVE_AT91_UTMI */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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