^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk/at91_pmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <soc/at91/atmel-sfr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "pmc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * The purpose of this clock is to generate a 480 MHz signal. A different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * rate can't be configured.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define UTMI_RATE 480000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct clk_utmi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct regmap *regmap_pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct regmap *regmap_sfr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define to_clk_utmi(hw) container_of(hw, struct clk_utmi, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static inline bool clk_utmi_ready(struct regmap *regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) regmap_read(regmap, AT91_PMC_SR, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return status & AT91_PMC_LOCKU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int clk_utmi_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct clk_hw *hw_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct clk_utmi *utmi = to_clk_utmi(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned int uckr = AT91_PMC_UPLLEN | AT91_PMC_UPLLCOUNT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) AT91_PMC_BIASEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned int utmi_ref_clk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned long parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * If mainck rate is different from 12 MHz, we have to configure the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * FREQ field of the SFR_UTMICKTRIM register to generate properly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * the utmi clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) hw_parent = clk_hw_get_parent(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) parent_rate = clk_hw_get_rate(hw_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) switch (parent_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) case 12000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) utmi_ref_clk_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) case 16000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) utmi_ref_clk_freq = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) case 24000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) utmi_ref_clk_freq = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * Not supported on SAMA5D2 but it's not an issue since MAINCK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * maximum value is 24 MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) case 48000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) utmi_ref_clk_freq = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) pr_err("UTMICK: unsupported mainck rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (utmi->regmap_sfr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) regmap_update_bits(utmi->regmap_sfr, AT91_SFR_UTMICKTRIM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) AT91_UTMICKTRIM_FREQ, utmi_ref_clk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) } else if (utmi_ref_clk_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) pr_err("UTMICK: sfr node required\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) regmap_update_bits(utmi->regmap_pmc, AT91_CKGR_UCKR, uckr, uckr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) while (!clk_utmi_ready(utmi->regmap_pmc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static int clk_utmi_is_prepared(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct clk_utmi *utmi = to_clk_utmi(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return clk_utmi_ready(utmi->regmap_pmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void clk_utmi_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct clk_utmi *utmi = to_clk_utmi(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) regmap_update_bits(utmi->regmap_pmc, AT91_CKGR_UCKR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) AT91_PMC_UPLLEN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static unsigned long clk_utmi_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* UTMI clk rate is fixed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return UTMI_RATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const struct clk_ops utmi_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .prepare = clk_utmi_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .unprepare = clk_utmi_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .is_prepared = clk_utmi_is_prepared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .recalc_rate = clk_utmi_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) at91_clk_register_utmi_internal(struct regmap *regmap_pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct regmap *regmap_sfr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) const struct clk_ops *ops, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct clk_utmi *utmi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) utmi = kzalloc(sizeof(*utmi), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (!utmi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) init.ops = ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) init.parent_names = parent_name ? &parent_name : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) init.num_parents = parent_name ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) init.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) utmi->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) utmi->regmap_pmc = regmap_pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) utmi->regmap_sfr = regmap_sfr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) hw = &utmi->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ret = clk_hw_register(NULL, &utmi->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) kfree(utmi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) const char *name, const char *parent_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return at91_clk_register_utmi_internal(regmap_pmc, regmap_sfr, name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) parent_name, &utmi_ops, CLK_SET_RATE_GATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int clk_utmi_sama7g5_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct clk_utmi *utmi = to_clk_utmi(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct clk_hw *hw_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned long parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) hw_parent = clk_hw_get_parent(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) parent_rate = clk_hw_get_rate(hw_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) switch (parent_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) case 16000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) case 20000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) val = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) case 24000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) val = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) case 32000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) val = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) pr_err("UTMICK: unsupported main_xtal rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) regmap_write(utmi->regmap_pmc, AT91_PMC_XTALF, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int clk_utmi_sama7g5_is_prepared(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct clk_utmi *utmi = to_clk_utmi(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct clk_hw *hw_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned long parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) hw_parent = clk_hw_get_parent(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) parent_rate = clk_hw_get_rate(hw_parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) regmap_read(utmi->regmap_pmc, AT91_PMC_XTALF, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) switch (val & 0x7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (parent_rate == 16000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (parent_rate == 20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (parent_rate == 24000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (parent_rate == 32000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const struct clk_ops sama7g5_utmi_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .prepare = clk_utmi_sama7g5_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .is_prepared = clk_utmi_sama7g5_is_prepared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .recalc_rate = clk_utmi_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) at91_clk_sama7g5_register_utmi(struct regmap *regmap_pmc, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) const char *parent_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return at91_clk_register_utmi_internal(regmap_pmc, NULL, name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) parent_name, &sama7g5_utmi_ops, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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