^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk/at91_pmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "pmc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SAM9X5_USB_DIV_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SAM9X5_USB_MAX_DIV 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RM9200_USB_DIV_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RM9200_USB_DIV_TAB_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SAM9X5_USBS_MASK GENMASK(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SAM9X60_USBS_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct at91sam9x5_clk_usb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u32 usbs_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u8 num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define to_at91sam9x5_clk_usb(hw) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) container_of(hw, struct at91sam9x5_clk_usb, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct at91rm9200_clk_usb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 divisors[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define to_at91rm9200_clk_usb(hw) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) container_of(hw, struct at91rm9200_clk_usb, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static unsigned long at91sam9x5_clk_usb_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned int usbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u8 usbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) regmap_read(usb->regmap, AT91_PMC_USB, &usbr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) usbdiv = (usbr & AT91_PMC_OHCIUSBDIV) >> SAM9X5_USB_DIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return DIV_ROUND_CLOSEST(parent_rate, (usbdiv + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int at91sam9x5_clk_usb_determine_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct clk_rate_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct clk_hw *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) long best_rate = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned long tmp_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int best_diff = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) int tmp_diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) parent = clk_hw_get_parent_by_index(hw, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (!parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) for (div = 1; div < SAM9X5_USB_MAX_DIV + 2; div++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned long tmp_parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) tmp_parent_rate = req->rate * div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) tmp_parent_rate = clk_hw_round_rate(parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) tmp_parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (!tmp_parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) tmp_rate = DIV_ROUND_CLOSEST(tmp_parent_rate, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (tmp_rate < req->rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) tmp_diff = req->rate - tmp_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) tmp_diff = tmp_rate - req->rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (best_diff < 0 || best_diff > tmp_diff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) best_rate = tmp_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) best_diff = tmp_diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) req->best_parent_rate = tmp_parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) req->best_parent_hw = parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (!best_diff || tmp_rate < req->rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (!best_diff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) if (best_rate < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return best_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) req->rate = best_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int at91sam9x5_clk_usb_set_parent(struct clk_hw *hw, u8 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (index >= usb->num_parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) regmap_update_bits(usb->regmap, AT91_PMC_USB, usb->usbs_mask, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static u8 at91sam9x5_clk_usb_get_parent(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned int usbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) regmap_read(usb->regmap, AT91_PMC_USB, &usbr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return usbr & usb->usbs_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int at91sam9x5_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned long div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (!rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) div = DIV_ROUND_CLOSEST(parent_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (div > SAM9X5_USB_MAX_DIV + 1 || !div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) regmap_update_bits(usb->regmap, AT91_PMC_USB, AT91_PMC_OHCIUSBDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) (div - 1) << SAM9X5_USB_DIV_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct clk_ops at91sam9x5_usb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .recalc_rate = at91sam9x5_clk_usb_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .determine_rate = at91sam9x5_clk_usb_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .get_parent = at91sam9x5_clk_usb_get_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .set_parent = at91sam9x5_clk_usb_set_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .set_rate = at91sam9x5_clk_usb_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static int at91sam9n12_clk_usb_enable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) regmap_update_bits(usb->regmap, AT91_PMC_USB, AT91_PMC_USBS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) AT91_PMC_USBS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static void at91sam9n12_clk_usb_disable(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) regmap_update_bits(usb->regmap, AT91_PMC_USB, AT91_PMC_USBS, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static int at91sam9n12_clk_usb_is_enabled(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned int usbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) regmap_read(usb->regmap, AT91_PMC_USB, &usbr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return usbr & AT91_PMC_USBS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const struct clk_ops at91sam9n12_usb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .enable = at91sam9n12_clk_usb_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .disable = at91sam9n12_clk_usb_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .is_enabled = at91sam9n12_clk_usb_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .recalc_rate = at91sam9x5_clk_usb_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .determine_rate = at91sam9x5_clk_usb_determine_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .set_rate = at91sam9x5_clk_usb_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) _at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) const char **parent_names, u8 num_parents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u32 usbs_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct at91sam9x5_clk_usb *usb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) usb = kzalloc(sizeof(*usb), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (!usb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) init.ops = &at91sam9x5_usb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) init.parent_names = parent_names;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) init.num_parents = num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) usb->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) usb->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) usb->usbs_mask = usbs_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) usb->num_parents = num_parents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) hw = &usb->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = clk_hw_register(NULL, &usb->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) kfree(usb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) const char **parent_names, u8 num_parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return _at91sam9x5_clk_register_usb(regmap, name, parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) num_parents, SAM9X5_USBS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) sam9x60_clk_register_usb(struct regmap *regmap, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) const char **parent_names, u8 num_parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return _at91sam9x5_clk_register_usb(regmap, name, parent_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) num_parents, SAM9X60_USBS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) at91sam9n12_clk_register_usb(struct regmap *regmap, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) const char *parent_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct at91sam9x5_clk_usb *usb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) usb = kzalloc(sizeof(*usb), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (!usb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) init.ops = &at91sam9n12_usb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) init.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) usb->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) usb->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) hw = &usb->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) ret = clk_hw_register(NULL, &usb->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) kfree(usb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static unsigned long at91rm9200_clk_usb_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned int pllbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u8 usbdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) regmap_read(usb->regmap, AT91_CKGR_PLLBR, &pllbr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) usbdiv = (pllbr & AT91_PMC_USBDIV) >> RM9200_USB_DIV_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (usb->divisors[usbdiv])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return parent_rate / usb->divisors[usbdiv];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static long at91rm9200_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct clk_hw *parent = clk_hw_get_parent(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned long bestrate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int bestdiff = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned long tmprate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) int tmpdiff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) for (i = 0; i < RM9200_USB_DIV_TAB_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) unsigned long tmp_parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (!usb->divisors[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) tmp_parent_rate = rate * usb->divisors[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) tmp_parent_rate = clk_hw_round_rate(parent, tmp_parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) tmprate = DIV_ROUND_CLOSEST(tmp_parent_rate, usb->divisors[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (tmprate < rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) tmpdiff = rate - tmprate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) tmpdiff = tmprate - rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) if (bestdiff < 0 || bestdiff > tmpdiff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) bestrate = tmprate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) bestdiff = tmpdiff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) *parent_rate = tmp_parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (!bestdiff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return bestrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int at91rm9200_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) unsigned long div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (!rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) div = DIV_ROUND_CLOSEST(parent_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) for (i = 0; i < RM9200_USB_DIV_TAB_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (usb->divisors[i] == div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) regmap_update_bits(usb->regmap, AT91_CKGR_PLLBR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) AT91_PMC_USBDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) i << RM9200_USB_DIV_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static const struct clk_ops at91rm9200_usb_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .recalc_rate = at91rm9200_clk_usb_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .round_rate = at91rm9200_clk_usb_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .set_rate = at91rm9200_clk_usb_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) at91rm9200_clk_register_usb(struct regmap *regmap, const char *name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) const char *parent_name, const u32 *divisors)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct at91rm9200_clk_usb *usb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) usb = kzalloc(sizeof(*usb), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (!usb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) init.ops = &at91rm9200_usb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) init.flags = CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) usb->hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) usb->regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) memcpy(usb->divisors, divisors, sizeof(usb->divisors));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) hw = &usb->hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ret = clk_hw_register(NULL, &usb->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) kfree(usb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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