^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2019 Microchip Technology Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk/at91_pmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "pmc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PMC_PLL_CTRL0_DIV_MSK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PMC_PLL_CTRL1_MUL_MSK GENMASK(31, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PMC_PLL_CTRL1_FRACR_MSK GENMASK(21, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PLL_DIV_MAX (FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, UINT_MAX) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define UPLL_DIV 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PLL_MUL_MAX (FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define FCORE_MIN (600000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define FCORE_MAX (1200000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PLL_MAX_ID 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct sam9x60_pll_core {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) spinlock_t *lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) const struct clk_pll_characteristics *characteristics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) const struct clk_pll_layout *layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct clk_hw hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct sam9x60_frac {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct sam9x60_pll_core core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 frac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u16 mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct sam9x60_div {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct sam9x60_pll_core core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u8 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define to_sam9x60_pll_core(hw) container_of(hw, struct sam9x60_pll_core, hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define to_sam9x60_frac(core) container_of(core, struct sam9x60_frac, core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define to_sam9x60_div(core) container_of(core, struct sam9x60_div, core)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static inline bool sam9x60_pll_ready(struct regmap *regmap, int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) regmap_read(regmap, AT91_PMC_PLL_ISR0, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return !!(status & BIT(id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static bool sam9x60_frac_pll_ready(struct regmap *regmap, u8 id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return sam9x60_pll_ready(regmap, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static unsigned long sam9x60_frac_pll_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct sam9x60_frac *frac = to_sam9x60_frac(core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return parent_rate * (frac->mul + 1) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) DIV_ROUND_CLOSEST_ULL((u64)parent_rate * frac->frac, (1 << 22));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int sam9x60_frac_pll_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct sam9x60_frac *frac = to_sam9x60_frac(core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct regmap *regmap = core->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned int val, cfrac, cmul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) spin_lock_irqsave(core->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) AT91_PMC_PLL_UPDT_ID_MSK, core->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) cfrac = (val & core->layout->frac_mask) >> core->layout->frac_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (sam9x60_frac_pll_ready(regmap, core->id) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) (cmul == frac->mul && cfrac == frac->frac))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Recommended value for PMC_PLL_ACR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (core->characteristics->upll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) val = AT91_PMC_PLL_ACR_DEFAULT_UPLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) val = AT91_PMC_PLL_ACR_DEFAULT_PLLA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) regmap_write(regmap, AT91_PMC_PLL_ACR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) regmap_write(regmap, AT91_PMC_PLL_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) (frac->mul << core->layout->mul_shift) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) (frac->frac << core->layout->frac_shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (core->characteristics->upll) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Enable the UTMI internal bandgap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) val |= AT91_PMC_PLL_ACR_UTMIBG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) regmap_write(regmap, AT91_PMC_PLL_ACR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Enable the UTMI internal regulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) val |= AT91_PMC_PLL_ACR_UTMIVR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) regmap_write(regmap, AT91_PMC_PLL_ACR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) AT91_PMC_PLL_UPDT_UPDATE | core->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) AT91_PMC_PLL_UPDT_UPDATE | core->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) while (!sam9x60_pll_ready(regmap, core->id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) spin_unlock_irqrestore(core->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static void sam9x60_frac_pll_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct regmap *regmap = core->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) spin_lock_irqsave(core->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) AT91_PMC_PLL_UPDT_ID_MSK, core->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, AT91_PMC_PLL_CTRL0_ENPLL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (core->characteristics->upll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) regmap_update_bits(regmap, AT91_PMC_PLL_ACR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) AT91_PMC_PLL_ACR_UTMIBG | AT91_PMC_PLL_ACR_UTMIVR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) AT91_PMC_PLL_UPDT_UPDATE | core->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) spin_unlock_irqrestore(core->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int sam9x60_frac_pll_is_prepared(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return sam9x60_pll_ready(core->regmap, core->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static long sam9x60_frac_pll_compute_mul_frac(struct sam9x60_pll_core *core,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned long parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) bool update)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct sam9x60_frac *frac = to_sam9x60_frac(core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned long tmprate, remainder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned long nmul = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned long nfrac = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (rate < FCORE_MIN || rate > FCORE_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * Calculate the multiplier associated with the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * divider that provide the closest rate to the requested one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) nmul = mult_frac(rate, 1, parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) tmprate = mult_frac(parent_rate, nmul, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) remainder = rate - tmprate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (remainder) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) nfrac = DIV_ROUND_CLOSEST_ULL((u64)remainder * (1 << 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) parent_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) tmprate += DIV_ROUND_CLOSEST_ULL((u64)nfrac * parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) (1 << 22));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Check if resulted rate is a valid. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (tmprate < FCORE_MIN || tmprate > FCORE_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (update) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) frac->mul = nmul - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) frac->frac = nfrac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return tmprate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static long sam9x60_frac_pll_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return sam9x60_frac_pll_compute_mul_frac(core, rate, *parent_rate, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static int sam9x60_frac_pll_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return sam9x60_frac_pll_compute_mul_frac(core, rate, parent_rate, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static const struct clk_ops sam9x60_frac_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .prepare = sam9x60_frac_pll_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .unprepare = sam9x60_frac_pll_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .is_prepared = sam9x60_frac_pll_is_prepared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .recalc_rate = sam9x60_frac_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .round_rate = sam9x60_frac_pll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .set_rate = sam9x60_frac_pll_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int sam9x60_div_pll_prepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct sam9x60_div *div = to_sam9x60_div(core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct regmap *regmap = core->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) unsigned int val, cdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) spin_lock_irqsave(core->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) AT91_PMC_PLL_UPDT_ID_MSK, core->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Stop if enabled an nothing changed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (!!(val & core->layout->endiv_mask) && cdiv == div->div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) goto unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) core->layout->div_mask | core->layout->endiv_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) (div->div << core->layout->div_shift) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) (1 << core->layout->endiv_shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) AT91_PMC_PLL_UPDT_UPDATE | core->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) while (!sam9x60_pll_ready(regmap, core->id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) spin_unlock_irqrestore(core->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static void sam9x60_div_pll_unprepare(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct regmap *regmap = core->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) spin_lock_irqsave(core->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) AT91_PMC_PLL_UPDT_ID_MSK, core->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) core->layout->endiv_mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) AT91_PMC_PLL_UPDT_UPDATE | core->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) spin_unlock_irqrestore(core->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int sam9x60_div_pll_is_prepared(struct clk_hw *hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct regmap *regmap = core->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) spin_lock_irqsave(core->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) AT91_PMC_PLL_UPDT_ID_MSK, core->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) spin_unlock_irqrestore(core->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return !!(val & core->layout->endiv_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static unsigned long sam9x60_div_pll_recalc_rate(struct clk_hw *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct sam9x60_div *div = to_sam9x60_div(core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return DIV_ROUND_CLOSEST_ULL(parent_rate, (div->div + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static long sam9x60_div_pll_compute_div(struct sam9x60_pll_core *core,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) unsigned long *parent_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) const struct clk_pll_characteristics *characteristics =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) core->characteristics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct clk_hw *parent = clk_hw_get_parent(&core->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned long tmp_rate, tmp_parent_rate, tmp_diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) long best_diff = -1, best_rate = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u32 divid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (!rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (rate < characteristics->output[0].min ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) rate > characteristics->output[0].max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) for (divid = 1; divid < core->layout->div_mask; divid++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) tmp_parent_rate = clk_hw_round_rate(parent, rate * divid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (!tmp_parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) tmp_rate = DIV_ROUND_CLOSEST_ULL(tmp_parent_rate, divid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) tmp_diff = abs(rate - tmp_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (best_diff < 0 || best_diff > tmp_diff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) *parent_rate = tmp_parent_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) best_rate = tmp_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) best_diff = tmp_diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (!best_diff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (best_rate < characteristics->output[0].min ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) best_rate > characteristics->output[0].max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return best_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static long sam9x60_div_pll_round_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) unsigned long *parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return sam9x60_div_pll_compute_div(core, parent_rate, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static int sam9x60_div_pll_set_rate(struct clk_hw *hw, unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) unsigned long parent_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct sam9x60_pll_core *core = to_sam9x60_pll_core(hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct sam9x60_div *div = to_sam9x60_div(core);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) div->div = DIV_ROUND_CLOSEST(parent_rate, rate) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static const struct clk_ops sam9x60_div_pll_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .prepare = sam9x60_div_pll_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .unprepare = sam9x60_div_pll_unprepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .is_prepared = sam9x60_div_pll_is_prepared,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .recalc_rate = sam9x60_div_pll_recalc_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .round_rate = sam9x60_div_pll_round_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .set_rate = sam9x60_div_pll_set_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) const char *name, const char *parent_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct clk_hw *parent_hw, u8 id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) const struct clk_pll_characteristics *characteristics,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) const struct clk_pll_layout *layout, bool critical)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct sam9x60_frac *frac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) unsigned long parent_rate, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (id > PLL_MAX_ID || !lock || !parent_hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) frac = kzalloc(sizeof(*frac), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (!frac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) init.ops = &sam9x60_frac_pll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) init.flags = CLK_SET_RATE_GATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (critical)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) init.flags |= CLK_IS_CRITICAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) frac->core.id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) frac->core.hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) frac->core.characteristics = characteristics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) frac->core.layout = layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) frac->core.regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) frac->core.lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) spin_lock_irqsave(frac->core.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (sam9x60_pll_ready(regmap, id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) AT91_PMC_PLL_UPDT_ID_MSK, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) frac->mul = FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) frac->frac = FIELD_GET(PMC_PLL_CTRL1_FRACR_MSK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * This means the PLL is not setup by bootloaders. In this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * case we need to set the minimum rate for it. Otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * a clock child of this PLL may be enabled before setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * its rate leading to enabling this PLL with unsupported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * rate. This will lead to PLL not being locked at all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) parent_rate = clk_hw_get_rate(parent_hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (!parent_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) hw = ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ret = sam9x60_frac_pll_compute_mul_frac(&frac->core, FCORE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) parent_rate, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (ret <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) goto free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) spin_unlock_irqrestore(frac->core.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) hw = &frac->core.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ret = clk_hw_register(NULL, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) kfree(frac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) spin_unlock_irqrestore(frac->core.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) kfree(frac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct clk_hw * __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) const char *name, const char *parent_name, u8 id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) const struct clk_pll_characteristics *characteristics,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) const struct clk_pll_layout *layout, bool critical)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct sam9x60_div *div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct clk_hw *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct clk_init_data init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (id > PLL_MAX_ID || !lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) div = kzalloc(sizeof(*div), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (!div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) init.name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) init.parent_names = &parent_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) init.num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) init.ops = &sam9x60_div_pll_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) CLK_SET_RATE_PARENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (critical)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) init.flags |= CLK_IS_CRITICAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) div->core.id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) div->core.hw.init = &init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) div->core.characteristics = characteristics;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) div->core.layout = layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) div->core.regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) div->core.lock = lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) spin_lock_irqsave(div->core.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) AT91_PMC_PLL_UPDT_ID_MSK, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) div->div = FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) spin_unlock_irqrestore(div->core.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) hw = &div->core.hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ret = clk_hw_register(NULL, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) kfree(div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) hw = ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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